Product Manuals

Fig. 1: The SLICE-FPGA-II

Model No. SLICE-FPGA-II
Document Last Updated on 2022/09/27 20:42

Please read Limited Warranty and General Warnings and Cautions prior to operating the SLICE-FPGA-II.

Click here for the Main Manuals Page.
Click here for the FFC-100 Quick Start Guide.
Click here for the FFC-100 Fiber Frequency Comb Manual Click here for the FFC-100 API.
Click here for the latest version of WinPython

The SLICE-FPGA-II is an FPGA based locking instrument for use with the FFC-100. Using the included software, the Carrier Envelope Offset and Optical frequencies of the FFC-100 can be locked with ease!

Note: All modules designed to be operated in a laboratory environment.

Fig. 2: Front Panel of the SLICE-FPGA-II

1. f_CEO input signal SMA
2. f_OPT input signal SMA
3. Current output for modulating pump diode on the FFC-100
4. PZT modulation output
5. Output for feeding an external reference clock, which can improve 10MHz timing on onboard oscillator. Use requires specifying input frequency in the settings menu.

Fig. 3: Back Panel of the SLICE-FPGA-II

1. AC power entry module and fuse
2. Currently Unused Extension port
3. Reference Clock signal (+3V 10MHz) for clocking external equipment
4. Analog Slow Servo control voltage (±10V)
5. Ethernet port for communication with a computer

• Open the “WinPython-64bit-3.6.1.0Qt5” folder after installing WinPython, and launch the Spyder application within this folder.
• Open the “digital_servo_python_gui_RPM100” folder and locate the GUI control file named “XEM_GUI3.py”.
• Drag and drop the file into Spyder, and run the script to launch the GUI.
• A start-up menu should appear (figure ??). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK.

• Navigate to the “Settings” tab and select the appropriate clock signal to be used. If using an external clock, type the frequency (in Hz) of your reference signal.

The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ_CEO to a reference and ƒ_OPT to a reference laser such as the Rio Planex. If you have not already done so, install WinPython for controlling the SLICE-FPGA-II.

Fig. 4: System Level Diagram of the SLICE-FPGA-II Connected to an FFC-100

Locking f_opt requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All performance data is collected with a Rio Planex laser.

1. Navigate to the “CEO Lock” tab and adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the the data in the Baseband IQ plot is circular and the beat note is visibly centered under the middle red filter arch (figure 5). It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment.
   Fig. 5: Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)
   
2. Press the “Lock” button (figure 6, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. If the system still won't lock, try lowering the K_p value (bottom left).
   Fig. 6: Locking ƒ(CEO)
   

1. Navigate to the “Optical Lock” window. Center the beat note near the reference frequency: adjust the “Offset DAC 1” slider (or your reference laser frequency) until you see a circular Baseband IQ diagram (figure 7).
   Fig. 7: Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)
   
2. Press the “Lock” button (figure 8). If ƒ_opt doesn’t lock, change the VCO sign to the opposite polarity and try again. If the system continues to not lock, lower the K_p value.Fig. 8: Locking ƒ(opt)
   
3. Adjust PID settings (bottom middle of figure 8) accordingly to lower the integrated phase noise of each parameter (f_CEO and f_opt). The default settings provided in the software are a good place to start but tweaking the values can often improve performance.

The external clock input (#5 on the Front Panel Diagram) is used to feed an external reference clock, which can be used to clock the SLICE-FPGA-IIs ADCs and generate the 10MHz reference signal which is normally generated with the internal oscillator. For example, the SLICE-FPGA-II can be clocked with an external reference, or the f_REP signal from the FFC-100. To use this feature, it is necessary to first specify the input frequency in the settings menu of the software provided with the SLICE-FPGA-II, under the “Target ExtClk Freq” box. Pressing ENTER after giving a value will apply the new clock settings.

Fig. 9: The settings screen of the SLICE-FPGA-II

The SLICE-FPGA-II will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference.

In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment. If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure.

Whatever ethernet port you use to control the SLICE-FPGA-II, it is necessary that your computer identifies itself on this Ethernet port with a fixed IP address in the 192.168.0.x subnet. Sometimes a computer’s default settings do not fit this requirement. From the Windows Control Panel, click through: Network and Internet –> Network and Sharing Center –> Change adapter settings

You will see a number of network adapters listed. You should see one of the network adapters change state when you connect the powered-on SLICE-FPGA-II to your PC via the ethernet cable, as shown below:

Watch for this change to identify the correct network adapter.

• Right-click on the adapter, and click Properties.
• From the screen that appears, click on “Internet Protocol Version 4 (TCP/IPv4)” and then click Properties.

Fig. 10: The Adapter Properties screen, with the IPv4 Settings highlighted

• In the IPv4 Properties Page, select the bubble next to “Use the following IP address:”, and fill in the IP Address to be 192.168.0.xxx, where xxx is an integer from 0 to 255, and not 150, as that is the address used by the SLICE-FPGA-II. In this example, we used 196.

Fig. 11: The IPv4 Properties page, with the IP Address and Subnet Mask filled in.

The Subnet Mask will default to 255.255.255.0, which is fine.

NOTE: If you use this same Ethernet port to connect to another network, these configuration changes could result in connectivity problems with that network. If this poses a problem for you, consider buying a USB-to-Ethernet adapter, and configuring just that adapter for use with the SLICE-FPGA-II.

If you continue to have trouble connecting to the SLICE-FPGA-II, it’s possible that your firewall settings are blocking communications with the device. From the Windows Control Panel, click on System and Security –> Windows Defender Firewall –> Advanced Settings to open up the Windows Defender Firewall with Advanced Security manager application. In the left panel of the program, click “Inbound Rules.” Then, in the right-hand panel of the program, click “New Rule…” Use the “New Inbound Rule Wizard” to create a new rule to the following specifications:

• Rule Type: Program
• Program: [WINPYTHON INSTALL DIRECTORY]\WinPython-64bit-3.6.1.0Qt5\python-3.6.1.amd64\python.exe
• Action: Allow the connection
• Profile: Domain, Private, and Public
• Name: Red Pitaya WinPython (or another name of your choice)

In the left-hand panel, click “Outbound Rules”, and then click “New Rule…”. Repeat the above Rule creation steps to create a rule that allows outgoing packets from the WinPython directory’s “python.exe” file. Finally, ensure that the aforementioned python.exe file is not being restricted by any other firewall rules.