Differences

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--- ffc:locking_electronics:rpm-100 [2022/09/27 20:16] – external edit 127.0.0.1
+++ ffc:locking_electronics:rpm-100 [2022/09/27 20:42] – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
-=====RPM-100 Manual=====
+=====SLICE-FPGA-II Manual=====
-<imgcaption stage_photo|The RPM-100>{{ :ffc:locking_electronics:rpm-100_stage_photo.jpg?300|}}</imgcaption>
+<imgcaption stage_photo|The SLICE-FPGA-II>{{ :ffc:locking_electronics:rpm-100_stage_photo.jpg?300|}}</imgcaption>
-Model No. RPM-100\\
+Model No. SLICE-FPGA-II\\
 Document Last Updated on ~~LASTMOD~~
-Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the RPM-100.
+Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the SLICE-FPGA-II.
-====Links====
+=====Links=====
 Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\
 Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\
@@ Line 17: / Line 17: @@
 =====Description=====
-The RPM-100 is an FPGA based locking instrument for use with the FFC-100. Using the included software, the Carrier Envelope Offset and Optical frequencies of the FFC-100 can be locked with ease!
+The SLICE-FPGA-II is an FPGA based locking instrument for use with the FFC-100. Using the included software, the Carrier Envelope Offset and Optical frequencies of the FFC-100 can be locked with ease!
 ===== List of Warning Symbols =====
@@ Line 44: / Line 44: @@
 | {{ :warning-sign.png?100&nolink }} |Do not block the airflow vents on the side of the chassis or the fan inputs & outputs on either the FFC-100 or the SLICE-FPGA. |
 |:::| If this instrument is used in a manner not specified by the manufacturer in this manual or other relevant literature, protection provided by the instrument may be impaired. |
-|:::| Successful implementation of the RPM-100 depends critically on the design of the whole system: FFC-100, phase locking electronics, and any references to which the FFC-100 is locked or //vice versa//. |
+|:::| Successful implementation of the SLICE-FPGA-II depends critically on the design of the whole system: FFC-100, phase locking electronics, and any references to which the FFC-100 is locked or //vice versa//. |
 =====Specifications=====
-<WRAP center round box 60%><tabcaption specs|Specifications of RPM-100 Inputs and Outputs>
+<WRAP center round box 60%><tabcaption specs|Specifications of SLICE-FPGA-II Inputs and Outputs>
 |  **Inputs**   ||||
 |||||
@@ Line 65: / Line 65: @@
 =====Front Panel=====
-<imgcaption front_panel|Front Panel of the RPM-100>{{ :ffc:locking_electronics:front_panel_markup.png?600 |}}</imgcaption>
+<imgcaption front_panel|Front Panel of the SLICE-FPGA-II>{{ :ffc:locking_electronics:front_panel_markup.png?600 |}}</imgcaption>
   -f<sub>CEO</sub> input signal SMA
@@ Line 75: / Line 75: @@
 =====Back Panel=====
-<imgcaption back_panel|Back Panel of the RPM-100>{{ :ffc:locking_electronics:back_panel_markup.png?600 |}}</imgcaption>
+<imgcaption back_panel|Back Panel of the SLICE-FPGA-II>{{ :ffc:locking_electronics:back_panel_markup.png?600 |}}</imgcaption>
   -AC power entry module and fuse
@@ Line 97: / Line 97: @@
 =====FPGA Control=====
-The RPM-100 FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex.
+The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex.
-If you have not already done so, install WinPython for controlling the RPM-100.
+If you have not already done so, install WinPython for controlling the SLICE-FPGA-II.
-<imgcaption diagramp|System Level Diagram of the RPM-100 Connected to an FFC-100>{{ :ffc:locking_electronics:red_pitaya_locked_comb_schematic.png?600 |}}</imgcaption>
+<imgcaption diagramp|System Level Diagram of the SLICE-FPGA-II Connected to an FFC-100>{{ :ffc:locking_electronics:red_pitaya_locked_comb_schematic.png?600 |}}</imgcaption>
 Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All performance data is collected with a Rio Planex laser.
@@ Line 120: / Line 120: @@
 ====External Clock====
-The external clock input (#5 on the [[ffc:locking_electronics:rpm-100#Front Panel|Front Panel Diagram]]) is used to feed an external reference clock, which can be used to clock the RPM-100s ADCs and generate the 10MHz reference signal which is normally generated with the internal oscillator. For example, the RPM-100 can be clocked with an external reference, or the f<sub>REP</sub> signal from the FFC-100. To use this feature, it is necessary to first specify the input frequency in the settings menu of the software provided with the RPM-100, under the "Target ExtClk Freq" box. Pressing ENTER after giving a value will apply the new clock settings.
+The external clock input (#5 on the [[ffc:locking_electronics:rpm-100#Front Panel|Front Panel Diagram]]) is used to feed an external reference clock, which can be used to clock the SLICE-FPGA-IIs ADCs and generate the 10MHz reference signal which is normally generated with the internal oscillator. For example, the SLICE-FPGA-II can be clocked with an external reference, or the f<sub>REP</sub> signal from the FFC-100. To use this feature, it is necessary to first specify the input frequency in the settings menu of the software provided with the SLICE-FPGA-II, under the "Target ExtClk Freq" box. Pressing ENTER after giving a value will apply the new clock settings.
-<imgcaption settings|The settings screen of the RPM-100>{{ :ffc:locking_electronics:settings.png?800 |}}</imgcaption>
+<imgcaption settings|The settings screen of the SLICE-FPGA-II>{{ :ffc:locking_electronics:settings.png?800 |}}</imgcaption>
-The RPM-100 will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference.
+The SLICE-FPGA-II will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference.
 =====Troubleshooting=====
 ====Overview====
-In many cases, all that is necessary to get up-and-running with the RPM-100 is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment.
+In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment.
-If you are unable to connect the GUI to the RPM-100, follow the below instructions to eliminate possible causes of failure.
+If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure.
 ====Ethernet Controller IP Configuration====
-Whatever ethernet port you use to control the RPM-100, it is necessary that your computer identifies itself on this Ethernet port with a fixed IP address in the **192.168.0.x subnet**.  Sometimes a computer’s default settings do not fit this requirement.
+Whatever ethernet port you use to control the SLICE-FPGA-II, it is necessary that your computer identifies itself on this Ethernet port with a fixed IP address in the **192.168.0.x subnet**.  Sometimes a computer’s default settings do not fit this requirement.
 From the Windows Control Panel, click through:
 Network and Internet --> Network and Sharing Center --> Change adapter settings
-You will see a number of network adapters listed.  You should see one of the network adapters change state when you connect the powered-on RPM-100 to your PC via the ethernet cable, as shown below:
+You will see a number of network adapters listed.  You should see one of the network adapters change state when you connect the powered-on SLICE-FPGA-II to your PC via the ethernet cable, as shown below:
 {{ :ffc:locking_electronics:ethernet.png?400 |}}
@@ Line 145: / Line 145: @@
 <imgcaption p2|The Adapter Properties screen, with the IPv4 Settings highlighted>{{ :ffc:locking_electronics:picture2.png?400 |}}</imgcaption>
-  *In the IPv4 Properties Page, select the bubble next to “Use the following IP address:”, and fill in the IP Address to be **192.168.0.xxx**, where **xxx** is an integer from 0 to 255, and not **150**, as that is the address used by the RPM-100.  In this example, we used 196.
+  *In the IPv4 Properties Page, select the bubble next to “Use the following IP address:”, and fill in the IP Address to be **192.168.0.xxx**, where **xxx** is an integer from 0 to 255, and not **150**, as that is the address used by the SLICE-FPGA-II.  In this example, we used 196.
 <imgcaption p3| The IPv4 Properties page, with the IP Address and Subnet Mask filled in.>{{ :ffc:locking_electronics:picture3.png?400 |}}</imgcaption>
@@ Line 151: / Line 151: @@
 The Subnet Mask will default to 255.255.255.0, which is fine.
-**NOTE:** If you use this same Ethernet port to connect to another network, these configuration changes could result in connectivity problems with that network.  If this poses a problem for you, consider buying a USB-to-Ethernet adapter, and configuring just that adapter for use with the RPM-100.
+**NOTE:** If you use this same Ethernet port to connect to another network, these configuration changes could result in connectivity problems with that network.  If this poses a problem for you, consider buying a USB-to-Ethernet adapter, and configuring just that adapter for use with the SLICE-FPGA-II.
 ====Windows Firewall Rules====
-If you continue to have trouble connecting to the RPM-100, it’s possible that your firewall settings are blocking communications with the device.
+If you continue to have trouble connecting to the SLICE-FPGA-II, it’s possible that your firewall settings are blocking communications with the device.
 From the Windows Control Panel, click on
 System and Security --> Windows Defender Firewall --> Advanced Settings