ffc:locking_electronics:rpm-100
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- | =====SLICE-FPGA-II Manual===== | ||
- | < | ||
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- | Model No. SLICE-FPGA-II\\ | ||
- | Document Last Updated on ~~LASTMOD~~ | ||
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- | Please read [[: | ||
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- | =====Links===== | ||
- | Click here for the [[http:// | ||
- | Click here for the [[ffc: | ||
- | Click here for the [[ffc: | ||
- | Click here for the [[ffc: | ||
- | Click here for the [[https:// | ||
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- | =====Description===== | ||
- | The SLICE-FPGA-II is an FPGA based locking instrument for use with the FFC-100. Using the included software, the Carrier Envelope Offset and Optical frequencies of the FFC-100 can be locked with ease! | ||
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- | ===== List of Warning Symbols ===== | ||
- | <WRAP center round box 60%> | ||
- | | {{ : | ||
- | | {{ : | ||
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- | </ | ||
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- | {{ ffc: | ||
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- | ===== Absolute Maximum Ratings and Power Input ===== | ||
- | Note: All modules designed to be operated in a laboratory environment. | ||
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- | <WRAP center round box 60%>< | ||
- | | **Parameter** | **Rating** | | ||
- | | Environmental Temperature | >15°C and <30°C| | ||
- | | Environmental Humidity | <60% | | ||
- | | Environmental Dew Points | <15°C | | ||
- | | Maximum AC Line Input Current | 2 A | | ||
- | </ | ||
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- | ===== Notice ===== | ||
- | | {{ : | ||
- | |:::| If this instrument is used in a manner not specified by the manufacturer in this manual or other relevant literature, protection provided by the instrument may be impaired. | | ||
- | |:::| Successful implementation of the SLICE-FPGA-II depends critically on the design of the whole system: FFC-100, phase locking electronics, | ||
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- | =====Specifications===== | ||
- | <WRAP center round box 60%>< | ||
- | | **Inputs** | ||
- | ||||| | ||
- | ^ Parameter | ||
- | | f< | ||
- | | f< | ||
- | | External Clock Input || 0dBm ((Do not exceed +10dBm for the protection of the device))|| | ||
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- | | **Outputs** || | ||
- | ^ Parameter | ||
- | | Current Out | ±10V | | ||
- | | PZT Out | 0V-5V | | ||
- | | | ||
- | | 10MHz Out | +3V TTL ((at 10MHz)) | | ||
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- | </ | ||
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- | =====Front Panel===== | ||
- | < | ||
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- | -f< | ||
- | -f< | ||
- | -Current output for modulating pump diode on the FFC-100 | ||
- | -PZT modulation output | ||
- | -Output for feeding an external reference clock, which can improve 10MHz timing on onboard oscillator. Use requires specifying input frequency in the settings menu. | ||
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- | =====Back Panel===== | ||
- | < | ||
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- | -AC power entry module and fuse | ||
- | -Currently Unused Extension port | ||
- | -Reference Clock signal (+3V 10MHz) for clocking external equipment | ||
- | -Analog Slow Servo control voltage (±10V) | ||
- | -Ethernet port for communication with a computer | ||
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- | =====Software Setup===== | ||
- | * Open the “WinPython-64bit-3.6.1.0Qt5” folder after installing WinPython, and launch the Spyder application within this folder. | ||
- | * Open the “digital_servo_python_gui_RPM100” folder and locate the GUI control file named “XEM_GUI3.py”. | ||
- | * Drag and drop the file into Spyder, and run the script to launch the GUI. | ||
- | * A start-up menu should appear (figure ??). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK. | ||
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- | {{ : | ||
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- | * Navigate to the “Settings” tab and select the appropriate clock signal to be used. If using an external clock, type the frequency (in Hz) of your reference signal. | ||
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- | {{ : | ||
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- | =====FPGA Control===== | ||
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- | The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ< | ||
- | If you have not already done so, install WinPython for controlling the SLICE-FPGA-II. | ||
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- | < | ||
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- | Locking f< | ||
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- | ==== Locking ƒ(CEO) ==== | ||
- | - Navigate to the “CEO Lock” tab and adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the the data in the Baseband IQ plot is circular and the beat note is visibly centered under the middle red filter arch (<imgref ceo_bbiq> | ||
- | - Press the “Lock” button (<imgref ceo_lock>, | ||
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- | ====Locking ƒ(opt)==== | ||
- | - Navigate to the “Optical Lock” window. | ||
- | {{ : | ||
- | - Press the “Lock” button (<imgref fopt_lock> | ||
- | - Adjust PID settings (bottom middle of <imgref fopt_lock> | ||
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- | ====External Clock==== | ||
- | The external clock input (#5 on the [[ffc: | ||
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- | < | ||
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- | The SLICE-FPGA-II will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference. | ||
- | =====Troubleshooting===== | ||
- | ====Overview==== | ||
- | In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, | ||
- | If you are unable to connect the GUI to the SLICE-FPGA-II, | ||
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- | ====Ethernet Controller IP Configuration==== | ||
- | Whatever ethernet port you use to control the SLICE-FPGA-II, | ||
- | From the Windows Control Panel, click through: | ||
- | Network and Internet --> Network and Sharing Center --> Change adapter settings | ||
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- | You will see a number of network adapters listed. | ||
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- | {{ : | ||
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- | Watch for this change to identify the correct network adapter. | ||
- | * Right-click on the adapter, and click **Properties**. | ||
- | * From the screen that appears, click on “Internet Protocol Version 4 (TCP/ | ||
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- | < | ||
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- | *In the IPv4 Properties Page, select the bubble next to “Use the following IP address: | ||
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- | < | ||
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- | The Subnet Mask will default to 255.255.255.0, | ||
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- | **NOTE:** If you use this same Ethernet port to connect to another network, these configuration changes could result in connectivity problems with that network. | ||
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- | ====Windows Firewall Rules==== | ||
- | If you continue to have trouble connecting to the SLICE-FPGA-II, | ||
- | From the Windows Control Panel, click on | ||
- | System and Security --> Windows Defender Firewall --> Advanced Settings | ||
- | to open up the **Windows Defender Firewall with Advanced Security** manager application. | ||
- | In the left panel of the program, click “Inbound Rules.” Then, in the right-hand panel of the program, click “New Rule…” | ||
- | Use the “New Inbound Rule Wizard” to create a new rule to the following specifications: | ||
- | * Rule Type: **Program** | ||
- | * Program: **[WINPYTHON INSTALL DIRECTORY]\WinPython-64bit-3.6.1.0Qt5\python-3.6.1.amd64\python.exe** | ||
- | * Action: **Allow the connection** | ||
- | * Profile: **Domain, Private, and Public** | ||
- | * Name: **Red Pitaya WinPython** (or another name of your choice) | ||
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- | In the left-hand panel, click “Outbound Rules”, and then click “New Rule…”. | ||
- | Repeat the above Rule creation steps to create a rule that allows outgoing packets from the WinPython directory’s “python.exe” file. | ||
- | Finally, ensure that the aforementioned python.exe file is not being restricted by any other firewall rules. | ||
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