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ice:oem_integration [2014/07/03 09:04]
Ben Luey fixed i2c superscript in link as it isn't supported.
ice:oem_integration [2020/03/05 17:55] (current)
Michael Radunsky
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 Considerations for integrating the ICE Platform stack in an OEM situation are detailed in the remainder of this document. Important key points include deciding on the type and quantity of daughter modules to use and how that relates to the overall power budget for both the power supply and the maximum currents that can be routed through the power bus. The mechanics of mounting the circuit boards and designing a thermal management system must also be designed. Connections for communication and I/O from the circuit boards to the integrator's system are also detailed in the document. Considerations for integrating the ICE Platform stack in an OEM situation are detailed in the remainder of this document. Important key points include deciding on the type and quantity of daughter modules to use and how that relates to the overall power budget for both the power supply and the maximum currents that can be routed through the power bus. The mechanics of mounting the circuit boards and designing a thermal management system must also be designed. Connections for communication and I/O from the circuit boards to the integrator's system are also detailed in the document.
 +
 +Can't find what you are looking for?  A [[https://groups.google.com/forum/#!forum/vescent-ice-qa|forum]] has been established for Q&A and information dissemination.  We invite you to join.
 ===== Power Requirements ===== ===== Power Requirements =====
 ==== Power Entry ==== ==== Power Entry ====
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 </WRAP> </WRAP>
  
-Power can be provided directly to the internal power bus headers if no master controller is used in the system, but this is highly discouraged as the power requirements are much more strict in order to prevent damaging system components. There are three power bus connectors shown in <imgref pcbSchematic> that utilize 0.1 inch double row board to board headers. The 6x2 headers ([[http://cloud.samtec.com/catalog_english/ESQ_TH.PDF|Samtec PN: ESQ-106-13-T-D]]) on either side of the pcb  carry 5V_A, +15V, +12V, -12V, -15V power rails and GND_A and GND signal. Both of the headers must be powered by the same power rails and be connected to the same grounds. The signal name GND_A is the return current path for the 5V_A rail which provides high current to daughter modules which require it (such as the [[ice:quadtemp|ICE-QT1]]). The 4x2 header ([[http://cloud.samtec.com/catalog_english/ESQ_TH.PDF|Samtec PN: ESQ-104-13-T-D]]) in the center of the pcb carries the digital communications bus and +5V_D power rail. The 5V_D power rail is designed to provide power to noisier digital components without contaminating the other analog power rails. This power rail can be "starred" off of the 5V_A line. All ground connections (GND, GND_A, GND_D) are intended to be starred at the power supply. The power sequence for turning on and off each voltage rail must be followed as described in the [[ice:oem_integration#power_sequencing|power sequencing section]] or damage will occur.+Power can be provided directly to the internal power bus headers if no master controller is used in the system, but this is highly discouraged as the power requirements are much more strict in order to prevent damaging system components. There are three power bus connectors shown in <imgref pcbSchematic> that utilize 0.1 inch double row board to board headers. The 6x2 headers ([[http://cloud.samtec.com/catalog_english/ESQ_TH.PDF|Samtec PN: ESQ-106-13-T-D]]) on either side of the PCB  carry 5V_A, +15V, +12V, -12V, -15V power rails and GND_A and GND signal. Both of the headers must be powered by the same power rails and be connected to the same grounds. The signal name GND_A is the return current path for the 5V_A rail which provides high current to daughter modules which require it (such as the [[ice:quadtemp|ICE-QT1]]). The 4x2 header ([[http://cloud.samtec.com/catalog_english/ESQ_TH.PDF|Samtec PN: ESQ-104-13-T-D]]) in the center of the PCB carries the digital communications bus and +5V_D power rail. The 5V_D power rail is designed to provide power to noisier digital components without contaminating the other analog power rails. This power rail can be "starred" off of the 5V_A line. All ground connections (GND, GND_A, GND_D) are intended to be starred at the power supply. The power sequence for turning on and off each voltage rail must be followed as described in the [[ice:oem_integration#power_sequencing|power sequencing section]] or damage will occur.
 ==== Power Draw by Module ==== ==== Power Draw by Module ====
-The power supply capacity for the supply used to power the ICE stack must be sized appropriately to handle expected power draw for the modules selected. Current draw is listed in the specifications for each of the daughter modules. The typical values indicate the quiescent current draw, and the max values represent worst case power draw depending on the functionality of the board. For example, the [[ice:quadtemp|ICE-QT1]] quad temperature controller has a maximum expected current draw on the 5V_A rail that depends on the maximum current supplied to thermo-electric coolers (TEC's). The maxiumum current here depends on what the user sets the current limit to for each temperature controller section. The max spec given is based on the highest current limit being set for each section, and the power supply should be capable of supply that current unless those current limits are set lower. Another example are the [[ice:servo-peaklock|ICE-CS1]] and [[ice:servo-opls|ICE-CP1]] modules, both of which include a laser current controller. The current draw on the +15V depends on the laser current output, which has a maximum output current that can be used to determine total current draw. This is detailed in the specifications charts on the respective product pages for all these modules.+The power supply capacity for the supply used to power the ICE stack must be sized appropriately to handle expected power draw for the modules selected. Current draw is listed in the specifications for each of the daughter modules. The typical values indicate the quiescent current draw, and the max values represent worst case power draw depending on the functionality of the board. For example, the [[ice:quadtemp|ICE-QT1]] quad temperature controller has a maximum expected current draw on the 5V_A rail that depends on the maximum current supplied to thermo-electric coolers (TEC's). The maximum current here depends on what the user sets the current limit to for each temperature controller section. The max spec given is based on the highest current limit being set for each section, and the power supply should be capable of supply that current unless those current limits are set lower. Another example are the [[ice:servo-peaklock|ICE-CS1]] and [[ice:servo-opls|ICE-CP1]] modules, both of which include a laser current controller. The current draw on the +15V depends on the laser current output, which has a maximum output current that can be used to determine total current draw. This is detailed in the specifications charts on the respective product pages for all these modules.
  
 The [[ice:master|ICE-MC1 master controller]] and ICE power bus have a maximum amount of current that can be routed. This is specified in the [[ice:master#specifications|maximum power consumption specification]] on the [[ice:master|ICE-MC1 product page]]. When choosing how many and which type of each daughter module a master controller can support, the expected current draw of all daughter modules must not exceed the maximum power consumption specification for the master controller. For example, the master controller and ICE power bus can only distribute a maximum of 10 amps on the 5V_A rail. If three [[ice:quadtemp|ICE-QT1]] temperature controllers were chosen as daughter modules, and all the TEC current limits were left at maximum, the three modules could potentially draw 12 amps. This would exceed the capacity of the power bus and master controller. The master controller provide over-current protection, so it would shut down power to the daughter modules and enter a fault condition if 12 amps were attempted to be drawn from the 5V_A rail. The [[ice:master|ICE-MC1 master controller]] and ICE power bus have a maximum amount of current that can be routed. This is specified in the [[ice:master#specifications|maximum power consumption specification]] on the [[ice:master|ICE-MC1 product page]]. When choosing how many and which type of each daughter module a master controller can support, the expected current draw of all daughter modules must not exceed the maximum power consumption specification for the master controller. For example, the master controller and ICE power bus can only distribute a maximum of 10 amps on the 5V_A rail. If three [[ice:quadtemp|ICE-QT1]] temperature controllers were chosen as daughter modules, and all the TEC current limits were left at maximum, the three modules could potentially draw 12 amps. This would exceed the capacity of the power bus and master controller. The master controller provide over-current protection, so it would shut down power to the daughter modules and enter a fault condition if 12 amps were attempted to be drawn from the 5V_A rail.
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 ==== Power Sequencing ==== ==== Power Sequencing ====
 +<WRAP center round info 60%>
 +Power sequencing is not required if using the [[ice:master|ICE-MC1 master controller]] as it handles sequencing and startup commands automatically.
 +</WRAP>
 +
 The ICE power bus that distributes power to all daughter modules must have each voltage rail properly sequenced when turning power on and off. The [[ice:master|ICE-MC1 master controller]] automatically takes care of this power sequencing to protect daughter modules. If power is being applied directly to the power bus by the OEM integrator, the power sequencing outlined in this section must strictly be followed to prevent damage to the daughter modules. Between each step, an appropriate amount of settling-time should given for the previous power rail to settle (fully turn on or off) before proceeding to the next step. This is generally at least 100 milliseconds for most power supplies and voltage regulators. The I<sup>2</sup>C broadcast commands are detailed in the [[ice:oem_integration#power_command_sequence|communications section]], but are included here to show the timing of when the commands should be sent. These commands are required to be sent for safe shutdown and proper operation of ICE daughter modules. The ICE power bus that distributes power to all daughter modules must have each voltage rail properly sequenced when turning power on and off. The [[ice:master|ICE-MC1 master controller]] automatically takes care of this power sequencing to protect daughter modules. If power is being applied directly to the power bus by the OEM integrator, the power sequencing outlined in this section must strictly be followed to prevent damage to the daughter modules. Between each step, an appropriate amount of settling-time should given for the previous power rail to settle (fully turn on or off) before proceeding to the next step. This is generally at least 100 milliseconds for most power supplies and voltage regulators. The I<sup>2</sup>C broadcast commands are detailed in the [[ice:oem_integration#power_command_sequence|communications section]], but are included here to show the timing of when the commands should be sent. These commands are required to be sent for safe shutdown and proper operation of ICE daughter modules.
  
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 |  8  |Wait 2.5 seconds | |  8  |Wait 2.5 seconds |
 |  9  |Broadcast System Ready I<sup>2</sup>C command((This command is detailed in the communications section)) | |  9  |Broadcast System Ready I<sup>2</sup>C command((This command is detailed in the communications section)) |
 +|  10  |Broadcast Interlock Off I<sup>2</sup>C command((This command is detailed in the communications section)) |
  
 === Power Off Sequence === === Power Off Sequence ===
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 </WRAP> </WRAP>
 Each PCB exposes up to 4 copper tabs to conduct heat out from power dissipating components to an external heat sink. The copper tabs are not electrically isolated, so electrical isolation is **required** at the interface between the heatsink and copper tab. Failure to isolate these tabs will result in malfunction of the ICE module. For electrical isolation with good thermal conductivity, [[http://www.bergquistcompany.com/thermal_materials/sil-pad.htm|Sil-Pad]] can be used. Sil-Pad requires a certain amount of pressure to ensure good thermal conductivity, so a clamp mechanism should be applied to the copper tabs. The Sil-Pad is shown in pink in <imgref thermalManagementSinglePCB> and <imgref thermalManagementClamp>. Each PCB exposes up to 4 copper tabs to conduct heat out from power dissipating components to an external heat sink. The copper tabs are not electrically isolated, so electrical isolation is **required** at the interface between the heatsink and copper tab. Failure to isolate these tabs will result in malfunction of the ICE module. For electrical isolation with good thermal conductivity, [[http://www.bergquistcompany.com/thermal_materials/sil-pad.htm|Sil-Pad]] can be used. Sil-Pad requires a certain amount of pressure to ensure good thermal conductivity, so a clamp mechanism should be applied to the copper tabs. The Sil-Pad is shown in pink in <imgref thermalManagementSinglePCB> and <imgref thermalManagementClamp>.
 +
 +Further information on thermal management of the ICE boards, including CAD drawings of the heat sink clamp assembly, can be [[http://cdn.vescent.com/wp-content/uploads/2014/07/ICE-OEM-Board-design-pack.zip?829774|downloaded here]].
  
 <WRAP center round important 60%> <WRAP center round important 60%>
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 <imgcaption thermalManagementClamp|Detail of a clamping mechanism used to conduct heat with electrical isolation.>{{ :ice:oem_heat_sinking_wedge_spec_-_image_07.png?600 |}}</imgcaption> <imgcaption thermalManagementClamp|Detail of a clamping mechanism used to conduct heat with electrical isolation.>{{ :ice:oem_heat_sinking_wedge_spec_-_image_07.png?600 |}}</imgcaption>
- 
 ==== Board Connections ==== ==== Board Connections ====
-Each ICE daughter module exposes analog interfaces on the side opposite to the copper heatsink tabs. Each module's circuit board may use a mixture of the connectors described in this section. Each connector and an associated part number shown below such that the OEM integrator my chose a suitable mating connector for their system. Consult the product pages for each ICE module to determine the type, position, and function of any connectors used.+Each ICE daughter module exposes analog interfaces on the side opposite to the copper heatsink tabs. Each module's circuit board may use a mixture of the connectors described in this section. Each connector and an associated part number shown below such that the OEM integrator my chose a suitable mating connector for their system. Consult the product pages for each ICE module to determine the type, position, and function of any connectors used. See the respective product pages for each OEM board for a diagram of the positioning of any connectors. 
 + 
 +For all ICE daughter modules, the circuit boards are designed such that all I/O connectors will be on a single side, and the copper heatsinking tabs will be on the opposite side. The master controller (ICE-MC1) also follows this convention, with the exception being the serial port flat flex connector.
  
 === Ultra-Miniature Coax Connector (UMCC) === === Ultra-Miniature Coax Connector (UMCC) ===
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 === Flat Flex Connector (FFC) === === Flat Flex Connector (FFC) ===
 These FFC connectors ([[http://www.digikey.com/product-detail/en/SFW12R-1STE1LF/609-1900-1-ND/1003179|FCI PN: SFW12R-1STE1LF]]) are used the [[ice:quadtemp|ICE-QT1]] to bring out the thermistor and TEC drive signals. Lower pin count ones are also used on the [[ice:master|ICE-MC1]] master controller for interfacing digital communications. Standard 1.00 mm pitch FFC jumper cables can be used to connect to an FFC connector on the other end. The ICE system uses right angle, 1.00 mm pitch, bottom contact FFC connectors. These FFC connectors ([[http://www.digikey.com/product-detail/en/SFW12R-1STE1LF/609-1900-1-ND/1003179|FCI PN: SFW12R-1STE1LF]]) are used the [[ice:quadtemp|ICE-QT1]] to bring out the thermistor and TEC drive signals. Lower pin count ones are also used on the [[ice:master|ICE-MC1]] master controller for interfacing digital communications. Standard 1.00 mm pitch FFC jumper cables can be used to connect to an FFC connector on the other end. The ICE system uses right angle, 1.00 mm pitch, bottom contact FFC connectors.
 +
 +<WRAP center round info 60%>
 +Generally, the minimum bend radius for flat flex jumper cables is 2mm. The length of the stiffener behind the exposed contacts on the cable will determine how far out from the FFC PCB connector the first bend of the flat flex cable can occur. The clearance for this bend must be accounted for when designing an enclosure for the ICE boards. For example, with Molex brand flat flex cables, there needs to be a minimum 0.25 inch clearance from the front of the flat flex PCB connector to allow the cable to bend. Verify against the data sheet of the chosen flat flex jumper cable.
 +</WRAP>
  
 <imgcaption ffcConnector|Surface mount, 12-pin, 1.00 mm pitch, bottom contact FFC connector. FCI PN: SFW12R-1STE1LF>{{ :ice:sfw12r-1ste1lf.jpg?300 |}}</imgcaption> <imgcaption ffcConnector|Surface mount, 12-pin, 1.00 mm pitch, bottom contact FFC connector. FCI PN: SFW12R-1STE1LF>{{ :ice:sfw12r-1ste1lf.jpg?300 |}}</imgcaption>
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 This section details considerations for communicating with ICE modules in the system. For pin definitions and types of connectors for interfacing with the ICE stack, refer to the [[ice:master|ICE-MC1 master controller product page]]. This section details considerations for communicating with ICE modules in the system. For pin definitions and types of connectors for interfacing with the ICE stack, refer to the [[ice:master|ICE-MC1 master controller product page]].
 ==== I2C Addressing ==== ==== I2C Addressing ====
-The ICE board stack uses an [[http://en.wikipedia.org/wiki/I%C2%B2C|I2C communication bus]] to control each board. I<sup>2</sup>C is an addressable protocal, therefore each ICE daughter module needs to have a unique address set. Up to 8 daughter modules (not including the [[ice:master|ICE-MC1]] master controller) can be stacked together. Each ICE circuit board has a 3 position DIP switch (shown in <imgref dipSwitch>) installed that allows the setting of each modules I<sup>2</sup>C address (between 0-7). The selection of address is in binary with DIP position 1 corresponding to the least significant bit. Setting a bit "HIGH" is done by sliding the switch to the side marked with the word "ON", which is shown highlighted in <imgref dipSwitchDiagram>. An example address setting is shown in <tabref i2cAddrEx>. Valid I<sup>2</sup>C addresses are from 0-7, and every ICE module must be set to have a unique address or communications bus collisions will occur.+The ICE board stack uses an [[http://en.wikipedia.org/wiki/I%C2%B2C|I2C communication bus]] to control each board. I<sup>2</sup>C is an addressable protocol, therefore each ICE daughter module needs to have a unique address set. Up to 8 daughter modules (not including the [[ice:master|ICE-MC1]] master controller) can be stacked together. Each ICE circuit board has a 3 position DIP switch (shown in <imgref dipSwitch>) installed that allows the setting of each modules I<sup>2</sup>C address (between 0-7). The selection of address is in binary with DIP position 1 corresponding to the least significant bit. Setting a bit "HIGH" is done by sliding the switch to the side marked with the word "ON", which is shown highlighted in <imgref dipSwitchDiagram>. An example address setting is shown in <tabref i2cAddrEx>. Valid I<sup>2</sup>C addresses are from 0-7, and every ICE module must be set to have a unique address or communications bus collisions will occur.
  
 <WRAP center> <WRAP center>
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-<imgcaption dipSwitch|Photo of I<sup>2</sup>address selection DIP switch.>{{ :ice:cvs-03tb.jpg?300 |}}</imgcaption>+<imgcaption dipSwitch|Photo of I2C address selection DIP switch.>{{ :ice:cvs-03tb.jpg?300 |}}</imgcaption>
  
 <imgcaption dipSwitchDiagram|The side which corresponds to ON or HIGH is highlighted in yellow.>{{ :ice:addressdipswitch.png |}}</imgcaption> <imgcaption dipSwitchDiagram|The side which corresponds to ON or HIGH is highlighted in yellow.>{{ :ice:addressdipswitch.png |}}</imgcaption>
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 When power up or shutting down the ICE modules, there are two I<sup>2</sup>C commands that must be sent. The [[ice:master|ICE-MC1 master controller]] automatically sends this commands and sequences the power rails, so sending this commands is not necessary if the ICE-MC1 is used. When power up or shutting down the ICE modules, there are two I<sup>2</sup>C commands that must be sent. The [[ice:master|ICE-MC1 master controller]] automatically sends this commands and sequences the power rails, so sending this commands is not necessary if the ICE-MC1 is used.
  
-At power on, once all voltage rails have been turned on and settled, the "System Ready" I<sup>2</sup>C command should be sent to the stack. It is advisable to wait at least 2.5 seconds after the last power rail has been turned on to send this command. See the [[ice:oem_integration#power_sequencing|power sequencing section]] for timing details. The ID of this command is 7 and takes no arguments. To send the command, send an I<sup>2</sup>C packet on one byte with the value of 0x07 to each ICE daughter module address (possible addresses are 0-7).+At power on, once all voltage rails have been turned on and settled, the "System Ready" I<sup>2</sup>C command should be sent to the stack. It is advisable to wait at least 2.5 seconds after the last power rail has been turned on to send this command. See the [[ice:oem_integration#power_sequencing|power sequencing section]] for timing details. The ID of this command is 7 and takes no arguments. To send the command, send an I<sup>2</sup>C packet on one byte with the value of 0x07 to each ICE daughter module address (possible addresses are 0-7). In addition, the "Interlock" command should be sent to allow all modules that have a laser current controller to turn on. The interlock command has an ID of 12 and an argument of 1. To send the command, send an I<sup>2</sup>C packet on two bytes with the value of [0x0C,0x01] to each ICE daughter module address (possible addresses are 0-7).
  
 Before turning off any voltage rails for shutdown, the "System Shutdown" Read I<sup>2</sup>C command should be sent to the stack. The ID of this command is 3 and takes no arguments. To send the command, send an I<sup>2</sup>C packet on one byte with the value of 0x03 to each ICE daughter module address (possible addresses are 0-7). This packet should be sent at least 1 second before turning off any power rails to give time for all ICE daughter modules to prepare for a clean shutdown. Again, see the [[ice:oem_integration#power_sequencing|power sequencing section]] for timing details. Before turning off any voltage rails for shutdown, the "System Shutdown" Read I<sup>2</sup>C command should be sent to the stack. The ID of this command is 3 and takes no arguments. To send the command, send an I<sup>2</sup>C packet on one byte with the value of 0x03 to each ICE daughter module address (possible addresses are 0-7). This packet should be sent at least 1 second before turning off any power rails to give time for all ICE daughter modules to prepare for a clean shutdown. Again, see the [[ice:oem_integration#power_sequencing|power sequencing section]] for timing details.
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 These raw I<sup>2</sup>C bus commands do not apply if using the [[ice:master|ICE-MC1 master controller]]. These raw I<sup>2</sup>C bus commands do not apply if using the [[ice:master|ICE-MC1 master controller]].
 </WRAP> </WRAP>
 +
 +==== Digital Communications Bus Header ====
 +<WRAP center round info 60%>
 +Details in this section do not apply if using the [[ice:master|ICE-MC1 master controller]].
 +</WRAP>
 +
 +The communications bus goes through a 0.1 inch board-to-board header located in the center of each ICE circuit board. See the <imgref pcbSchematic> for the pin definitions. If connecting directly to the ICE board stack without using an [[ice:master|ICE-MC1 master controller]], external pull-up resistors must be implemented by the OEM integrator on all the communication signals in this header (SDA, SCL, GPIO 1-4). The OEM integrator should use 1kΩ resistors pulled up to 3.3V on all these lines. The GPIO event bus lines are active low, but must float high when not in use. The SDA and SCL signals for the I<sup>2</sup>C bus must always have pull up resistors no bigger than 1kΩ.
  
ice/oem_integration.1404403485.txt.gz · Last modified: 2014/07/03 07:04 (external edit)