Differences

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--- ffc:locking_electronics:slice-fpga-ii [2023/06/09 21:08] – external edit 127.0.0.1
+++ ffc:locking_electronics:slice-fpga-ii [2023/08/09 00:20] (current) – external edit 127.0.0.1
@@ Line 13: / Line 13: @@
 Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\
 Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\
-Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\
+/*Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\ */
 Click here for the [[ffc:100:API|FFC-100 API]].\\
@@ Line 98: / Line 98: @@
 <imgcaption winpython|Start-up Menu>{{ :ffc:locking_electronics:winpython_terminal.png?700 |}}</imgcaption>
-  * A start-up menu should appear (<imgref startup>). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK.
+  * A start-up menu should appear (<imgref startup>). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device.
   *  If your computer does not see the SLICE-FPGA-II in the start up screen, consult the [[ffc:locking_electronics:slice-fpga-ii#troubleshooting|troubleshooting guide]] for additional help.
 <imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:start_window_marked.png?700 |}}</imgcaption>
+  * If you received your SLICE FPGA prior to 7/20/23, ensure “Push default values to Red Pitaya” is selected and press OK.
+  * If you received your SLICE FPGA after 7/20/23, ensure the center option is selected, labeled "Connect to a Red Pitaya with its current settings". If the default values of your SLICE FPGA II have been overwritten, the original values can be recovered by importing the XML file titled with your devices serial number. To do this, once connected to the FPGA, open the settings tab. In the Settings Management window enter the proper filename corresponding to your FFC serial number, and click "Import All Settings from File" (<imgref startup>).
+<imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:fpga_xml_import.png?200 |}}</imgcaption>
 =====FPGA Control=====
@@ Line 129: / Line 133: @@
   - Navigate to the “Optical Lock” window and enable the “Auto-refresh” button in the top left of the window. Set your desired RF lock frequency of the ƒ<sub>opt</sub> beatnote in the “Reference Frequency [Hz]” input. Adjust the “Offset DAC 1” slider near the top left by clicking and dragging the slider until the Beatnote is roughly centered in the red filter trace (<imgref opt_bbiq>).
   - Note: If parts of the GUI window are cutoff, shift the window out of full screen and press the maximize window button. \\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>
-{{ :ffc:locking_electronics:fopt_1_no-lock.png?800 |}}</imgcaption>\\
+{{ :ffc:locking_electronics:updated_centering_fopt.png?800 |}}</imgcaption>\\
-  - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:fopt_2_locked.png?800 |}}</imgcaption>\\
+  - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:updated_locking_fopt.png?800 |}}</imgcaption>\\
   - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC.
-  - Adjust PID settings (bottom of <imgref fceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment.
+  - Adjust PID settings (bottom of <imgref ceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment.
 =====Troubleshooting=====
 ====Overview====
-In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment.
+In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython terminal.
 If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure.