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--- ffc:locking_electronics:slice-fpga-ii [2023/06/09 20:00] – external edit 127.0.0.1
+++ ffc:locking_electronics:slice-fpga-ii [2023/08/09 00:20] (current) – external edit 127.0.0.1
@@ Line 13: / Line 13: @@
 Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\
 Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\
-Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\
+/*Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\ */
 Click here for the [[ffc:100:API|FFC-100 API]].\\
@@ Line 98: / Line 98: @@
 <imgcaption winpython|Start-up Menu>{{ :ffc:locking_electronics:winpython_terminal.png?700 |}}</imgcaption>
-  * A start-up menu should appear (<imgref startup>). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK.
+  * A start-up menu should appear (<imgref startup>). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device.
   *  If your computer does not see the SLICE-FPGA-II in the start up screen, consult the [[ffc:locking_electronics:slice-fpga-ii#troubleshooting|troubleshooting guide]] for additional help.
 <imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:start_window_marked.png?700 |}}</imgcaption>
-  * Navigate to the “Settings” tab and select the appropriate clock signal to be used (<imgref settings>). If using an external clock, type the frequency (in Hz) of your reference signal.
+  * If you received your SLICE FPGA prior to 7/20/23, ensure “Push default values to Red Pitaya” is selected and press OK.
-  * Note: The SLICE-FPGA-II accepts a variety of discrete clock signal frequencies (15, 20, 25, 30, 40, 50, 75, 100, 125, 150, 200 and 250 MHz). Due to limitations of the internal dividers of the FPGA, certain external clock frequencies will result in an inaccurate absolute frequency reference. If a clock frequency other than those provided is required, please contact Vescent staff to discuss your application.
+  * If you received your SLICE FPGA after 7/20/23, ensure the center option is selected, labeled "Connect to a Red Pitaya with its current settings". If the default values of your SLICE FPGA II have been overwritten, the original values can be recovered by importing the XML file titled with your devices serial number. To do this, once connected to the FPGA, open the settings tab. In the Settings Management window enter the proper filename corresponding to your FFC serial number, and click "Import All Settings from File" (<imgref startup>).
-<imgcaption settings|Settings Tab>{{ :ffc:locking_electronics:settings_marked.png?600 |}}</imgcaption>
+<imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:fpga_xml_import.png?200 |}}</imgcaption>
 =====FPGA Control=====
-The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex.
+The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex. The SLICE-FPGA-II should be connected to a Vescent frequency comb (FFC or Comb Module) as shown below (<imgref diagramp>).
 <imgcaption diagramp|System Level Diagram of the SLICE-FPGA-II Connected to an FFC-100>{{ :ffc:locking_electronics:red_pitaya_locked_comb_schematic.png?600 |}}</imgcaption>
-Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All performance data is collected with a Rio Planex laser.
+Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All Vescent performance data is collected with a Rio Planex laser.
+====External Clock====
+The external clock input (#5 on the [[ffc:locking_electronics:slice-fpga-II#Front Panel|Front Panel Diagram]]) allows the FPGA to be clocked with an external source, e.g. fREP from the FFC, or another system’s master clock. Navigate to the “Settings” tab and select the appropriate clock signal to be used (<imgref settings>). Enter the incoming clock’s frequency (in Hz) into the “Target ExtClk Freq” box, press enter, and then press the “External clock” button above
+<imgcaption settings|Settings Tab>{{ :ffc:locking_electronics:settings_marked.png?600 |}}</imgcaption>
+The SLICE-FPGA-II accepts a variety of discrete clock signal frequencies (15, 20, 25, 30, 40, 50, 75, 100, 125, 150, 200 and 250 MHz). Due to limitations of the internal dividers of the FPGA, certain external clock frequencies will result in an inaccurate absolute frequency reference. If a clock frequency other than those provided is required, please contact Vescent staff to discuss your application.
 ==== Locking ƒ(CEO) ====
-  - Navigate to the “CEO Lock” tab and adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the data in the Baseband IQ plot is circular and the beat note is visibly centered under the middle red filter band(<imgref ceo_bbiq>). It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment.\\ <imgcaption ceo_bbiq|Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)>{{ :ffc:locking_electronics:fceo_2_centered.png?800 |}}</imgcaption>\\
+  -Navigate to the “CEO Lock” tab and enable the “Auto-refresh” button in the top left of the window. Set your desired RF lock frequency of the Fceo beatnote in the “Reference Frequency [Hz]” input. Adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the Beatnote is roughly centered in the red filter trace (<imgref ceo_bbiq>). It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment.
-  - Press the “Lock” button (<imgref ceo_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom left).\\ <imgcaption ceo_lock|Locking ƒ(CEO)>{{ :ffc:locking_electronics:fceo_3_locked.png?800 |}}</imgcaption>\\
+  -Note: If parts of the FPGA GUI window are cutoff, shift the window out of full screen and press the maximize window button.<imgcaption ceo_bbiq|Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)>{{ :ffc:locking_electronics:updated_centering_fceo.png?800 |}}</imgcaption>\\
+  - Press the “Lock” button (<imgref ceo_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom left).<imgcaption ceo_lock|Locking ƒ(CEO)>{{ :ffc:locking_electronics:updated_locking_fceo.png?800 |}}</imgcaption>
+  - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC.
 ====Locking ƒ(opt)====
-  - Navigate to the “Optical Lock” window.  Center the beat note near the reference frequency: adjust the “Offset DAC 1” slider (or your reference laser frequency) until you see a circular Baseband IQ diagram (<imgref opt_bbiq>).\\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>
+  - Ensure that your laser reference source is properly mixed with the “EDFA Out” optical port of the frequency comb as described in the devices CoC and is input back into the device via the “ƒ<sub>opt</sub>” input port at a power level of <1.5 mW.
-{{ :ffc:locking_electronics:fopt_1_no-lock.png?800 |}}</imgcaption>\\
+  - Navigate to the “Optical Lock” window and enable the “Auto-refresh” button in the top left of the window. Set your desired RF lock frequency of the ƒ<sub>opt</sub> beatnote in the “Reference Frequency [Hz]” input. Adjust the “Offset DAC 1” slider near the top left by clicking and dragging the slider until the Beatnote is roughly centered in the red filter trace (<imgref opt_bbiq>).
-  - Press the “Lock” button (<imgref fopt_lock>). If ƒ<sub>opt</sub> doesn’t lock, change the VCO sign to the opposite polarity and try again. If the system continues to not lock, lower the K<sub>p</sub> value.<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:fopt_2_locked.png?800 |}}</imgcaption>\\
+  - Note: If parts of the GUI window are cutoff, shift the window out of full screen and press the maximize window button. \\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>
-  - Adjust PID settings (bottom middle of <imgref fopt_lock>) accordingly to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are a good place to start but tweaking the values can often improve performance.
+{{ :ffc:locking_electronics:updated_centering_fopt.png?800 |}}</imgcaption>\\
+  - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:updated_locking_fopt.png?800 |}}</imgcaption>\\
+  - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC.
-====External Clock====
+  - Adjust PID settings (bottom of <imgref ceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment.
-The external clock input (#5 on the [[ffc:locking_electronics:slice-fpga-II#Front Panel|Front Panel Diagram]]) allows the FPGA to be clocked with an external source, e.g. fREP from the FFC, or another system’s master clock. Enter the incoming clock’s frequency (in Hz) into the “Target ExtClk Freq” box, press enter, and then press the “External clock” button above. For example, the SLICE-FPGA-II can be clocked with an external reference, or the f<sub>REP</sub> signal from the FFC-100. To use this feature, it is necessary to first specify the input frequency in the settings menu of the software provided with the SLICE-FPGA-II, under the "Target ExtClk Freq" box. Pressing ENTER after giving a value will apply the new clock settings.
-<imgcaption settings|The settings screen of the SLICE-FPGA-II>{{ :ffc:locking_electronics:settings.png?800 |}}</imgcaption>
-The SLICE-FPGA-II will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference.
 =====Troubleshooting=====
 ====Overview====
-In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment.
+In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython terminal.
 If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure.