Product Manuals

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=====SLICE-FPGA-II Manual=====


Model No. SLICE-FPGA-II\\
Document Last Updated on ~~LASTMOD~~


Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the SLICE-FPGA-II.

<imgcaption stage_photo|The SLICE-FPGA-II>{{:ffc:locking_electronics:fpgaii_front_pic.jpg?direct&500| }}</imgcaption>\\

=====Links=====
Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\
Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\
/*Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\ */
Click here for the [[ffc:100:API|FFC-100 API]].\\

=====Description=====
The SLICE-FPGA-II is an FPGA-based locking instrument for use with a Fiber Frequency Comb such as the FFC-100. The included software allows for seamless locking of both the Carrier Envelope Offset and Optical frequencies.

==== Contents ====
The contents of the SLICE-FPGA-II box includes
   * SLICE-FPGA-II 
   * USB memory stick with WinPython-64bit-3.6.1.0Qt5 and control software
   * Power cord for your ship-to country
   * An Ethernet cable for connecting your SLICE-FPGA-II to a computer.

Ensure that you received all of the materials.  If you did not receive all of the materials, contact us at [[info@vescent.com|info@vescent.com]]

===== List of Warning Symbols =====
<WRAP center round box 60%>
| {{ :warning-sign.png?100&nolink }}    | Warning.  Pay special attention to procedures and notes.  If procedure is not followed carefully, damage to the SLICE-FPGA-II or devices connected to it may occur.  |
| {{ :electric_shock.png?100&nolink }}  | Potential for electrical shock hazard.                                                                                                                           |

</WRAP>




===== Absolute Maximum Ratings and Power Input =====
Note: All modules designed to be operated in a laboratory environment.

<WRAP center round box 60%><tabcaption abs_max_rat |Absolute Maximum Ratings>
| **Parameter** | **Rating** |
| Environmental Temperature | 15°C<T<30°C|
| Environmental Humidity | <60% | 
| Environmental Dew Points | <15°C |
| Maximum AC Line Input Current | 2 A |
</tabcaption></WRAP>

===== Notice =====
| {{ :warning-sign.png?100&nolink }} |Do not block the airflow vents on the side of the chassis or the fan inputs & outputs on either the FFC-100 or the SLICE-FPGA-II. |
|:::| If this instrument is used in a manner not specified by the manufacturer in this manual or other relevant literature, protection provided by the instrument may be impaired. |
|:::| Successful implementation of the SLICE-FPGA-II depends critically on the design of the whole system: Frequency Comb, phase locking electronics, and any references to which the Frequency Comb is locked or //vice versa//. |

=====Specifications=====
<WRAP center round box 60%><tabcaption specs|Specifications of SLICE-FPGA-II Inputs and Outputs>
|  **Inputs**   |||| 
|||||                                                                                                                                                             
^  Parameter  ^^  Value  ^^                                                                                                                                                                                                                                                                                                                                                                                                                                          
| f<sub>OPT</sub> || -30 ~ -15dBm||
| f<sub>CEO</sub> || -30 ~ -15dBm||
| External Clock Input || 0dBm ((Do not exceed +10dBm for the protection of the device))||

| **Outputs** ||                                                                                                                                                                                                                                                                                                             
^  Parameter  ^ Value ^ 
|  Current Out  |  ±10V  | 
|  PZT Out      | 0-5V |
|   Analog Slow Servo    | ±10V |
|   10MHz Out    | +3V TTL ((at 10MHz)) | 
|||           
</tabcaption></WRAP>

=====Front Panel=====
<imgcaption front_panel|Front Panel of the SLICE-FPGA-II>{{ :ffc:locking_electronics:slice-fpga-ii_front_panel.png?600 |}}</imgcaption>

  -f<sub>CEO</sub> input (SMA)
  -f<sub>OPT</sub> input (SMA)
  -Current output for modulating pump diode
  -PZT modulation output to modulate PZT
  -External Clock Input. Use requires specifying input frequency in the settings menu.


=====Back Panel=====
<imgcaption back_panel|Back Panel of the SLICE-FPGA-II>{{ :ffc:locking_electronics:SLICE-FPGA-II-rear.png?600 |}}</imgcaption>

  -AC power entry module and fuse
  -Extension port (unused)
  -Reference Clock signal (+3V 10MHz) for clocking external equipment
  -Analog Slow Servo control voltage (±10V)
  -Ethernet port for communication with a computer

=====Software Setup=====
  * Install WinPython (WinPython-64bit-3.6.1.0Qt5) from the USB memory stick provided with the SLICE-FPGA-II in an easy to remember location. Do not use "WinPython-64bit-3.6.1.0Qt5" from the sourceforge.net or Github.net websites.
  * Open the WinPython folder after installing WinPython, and launch the WinPython terminal within this folder.
  * Navigate to the “digital_servo_python_SLICE-FPGA-II” folder and type “python XEM_GUI3.py” to start the GUI.

<imgcaption winpython|Start-up Menu>{{ :ffc:locking_electronics:winpython_terminal.png?700 |}}</imgcaption>

  * A start-up menu should appear (<imgref startup>). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. 
  *  If your computer does not see the SLICE-FPGA-II in the start up screen, consult the [[ffc:locking_electronics:slice-fpga-ii#troubleshooting|troubleshooting guide]] for additional help.

<imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:start_window_marked.png?700 |}}</imgcaption>

  * If you received your SLICE FPGA prior to 7/20/23, ensure “Push default values to Red Pitaya” is selected and press OK.
  * If you received your SLICE FPGA after 7/20/23, ensure the center option is selected, labeled "Connect to a Red Pitaya with its current settings". If the default values of your SLICE FPGA II have been overwritten, the original values can be recovered by importing the XML file titled with your devices serial number. To do this, once connected to the FPGA, open the settings tab. In the Settings Management window enter the proper filename corresponding to your FFC serial number, and click "Import All Settings from File" (<imgref startup>).

<imgcaption startup|Start-up Menu>{{ :ffc:locking_electronics:fpga_xml_import.png?200 |}}</imgcaption>
=====FPGA Control=====

The SLICE-FPGA-II FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex. The SLICE-FPGA-II should be connected to a Vescent frequency comb (FFC or Comb Module) as shown below (<imgref diagramp>).

<imgcaption diagramp|System Level Diagram of the SLICE-FPGA-II Connected to an FFC-100>{{ :ffc:locking_electronics:red_pitaya_locked_comb_schematic.png?600 |}}</imgcaption>

Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All Vescent performance data is collected with a Rio Planex laser.

====External Clock====
The external clock input (#5 on the [[ffc:locking_electronics:slice-fpga-II#Front Panel|Front Panel Diagram]]) allows the FPGA to be clocked with an external source, e.g. fREP from the FFC, or another system’s master clock. Navigate to the “Settings” tab and select the appropriate clock signal to be used (<imgref settings>). Enter the incoming clock’s frequency (in Hz) into the “Target ExtClk Freq” box, press enter, and then press the “External clock” button above

<imgcaption settings|Settings Tab>{{ :ffc:locking_electronics:settings_marked.png?600 |}}</imgcaption>

The SLICE-FPGA-II accepts a variety of discrete clock signal frequencies (15, 20, 25, 30, 40, 50, 75, 100, 125, 150, 200 and 250 MHz). Due to limitations of the internal dividers of the FPGA, certain external clock frequencies will result in an inaccurate absolute frequency reference. If a clock frequency other than those provided is required, please contact Vescent staff to discuss your application.


==== Locking ƒ(CEO) ====
  -Navigate to the “CEO Lock” tab and enable the “Auto-refresh” button in the top left of the window. Set your desired RF lock frequency of the Fceo beatnote in the “Reference Frequency [Hz]” input. Adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the Beatnote is roughly centered in the red filter trace (<imgref ceo_bbiq>). It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment. 
  -Note: If parts of the FPGA GUI window are cutoff, shift the window out of full screen and press the maximize window button.<imgcaption ceo_bbiq|Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)>{{ :ffc:locking_electronics:updated_centering_fceo.png?800 |}}</imgcaption>\\
  - Press the “Lock” button (<imgref ceo_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom left).<imgcaption ceo_lock|Locking ƒ(CEO)>{{ :ffc:locking_electronics:updated_locking_fceo.png?800 |}}</imgcaption>
  - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC.

====Locking ƒ(opt)====
  - Ensure that your laser reference source is properly mixed with the “EDFA Out” optical port of the frequency comb as described in the devices CoC and is input back into the device via the “ƒ<sub>opt</sub>” input port at a power level of <1.5 mW.
  - Navigate to the “Optical Lock” window and enable the “Auto-refresh” button in the top left of the window. Set your desired RF lock frequency of the ƒ<sub>opt</sub> beatnote in the “Reference Frequency [Hz]” input. Adjust the “Offset DAC 1” slider near the top left by clicking and dragging the slider until the Beatnote is roughly centered in the red filter trace (<imgref opt_bbiq>).
  - Note: If parts of the GUI window are cutoff, shift the window out of full screen and press the maximize window button. \\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>
{{ :ffc:locking_electronics:updated_centering_fopt.png?800 |}}</imgcaption>\\
  - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:updated_locking_fopt.png?800 |}}</imgcaption>\\ 
  - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC.
  - Adjust PID settings (bottom of <imgref ceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment. 

=====Troubleshooting=====
====Overview====
In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython terminal.
If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure.

====Ethernet Controller IP Configuration====
Whatever ethernet port you use to control the SLICE-FPGA-II, it is necessary that your computer identifies itself on this Ethernet port with a fixed IP address in the **192.168.0.x subnet**.  Sometimes a computer’s default settings do not fit this requirement.
From the Windows Control Panel, click through:
Network and Internet --> Network and Sharing Center --> Change adapter settings

You will see a number of network adapters listed.  You should see one of the network adapters change state when you connect the powered-on SLICE-FPGA-II to your PC via the ethernet cable, as shown below:

{{ :ffc:locking_electronics:ethernet.png?400 |}}

Watch for this change to identify the correct network adapter.
  * Right-click on the adapter, and click **Properties**.
  * From the screen that appears, click on “Internet Protocol Version 4 (TCP/IPv4)” and then click Properties.

<imgcaption p2|The Adapter Properties screen, with the IPv4 Settings highlighted>{{ :ffc:locking_electronics:picture2.png?400 |}}</imgcaption>

  *In the IPv4 Properties Page, select the bubble next to “Use the following IP address:”, and fill in the IP Address to be **192.168.0.xxx**, where **xxx** is an integer from 0 to 255, and not **150**, as that is the address used by the SLICE-FPGA-II.  In this example, we used 196.

<imgcaption p3| The IPv4 Properties page, with the IP Address and Subnet Mask filled in.>{{ :ffc:locking_electronics:picture3.png?400 |}}</imgcaption>

The Subnet Mask will default to 255.255.255.0, which is fine.

**NOTE:** If you use this same Ethernet port to connect to another network, these configuration changes could result in connectivity problems with that network.  If this poses a problem for you, consider buying a USB-to-Ethernet adapter, and configuring just that adapter for use with the SLICE-FPGA-II.

====Windows Firewall Rules====
If you continue to have trouble connecting to the SLICE-FPGA-II, it’s possible that your firewall settings are blocking communications with the device.
From the Windows Control Panel, click on
System and Security --> Windows Defender Firewall --> Advanced Settings
to open up the **Windows Defender Firewall with Advanced Security** manager application.
In the left panel of the program, click “Inbound Rules.” Then, in the right-hand panel of the program, click “New Rule…”
Use the “New Inbound Rule Wizard” to create a new rule to the following specifications:
  * Rule Type: **Program**
  * Program: **[WINPYTHON INSTALL DIRECTORY]\WinPython-64bit-3.6.1.0Qt5\python-3.6.1.amd64\python.exe**
  * Action: **Allow the connection**
  * Profile: **Domain, Private, and Public**
  * Name: **Red Pitaya WinPython** (or another name of your choice)

In the left-hand panel, click “Outbound Rules”, and then click “New Rule…”.
Repeat the above Rule creation steps to create a rule that allows outgoing packets from the WinPython directory’s “python.exe” file.
Finally, ensure that the aforementioned python.exe file is not being restricted by any other firewall rules.