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ffc:fpga [2022/09/21 15:23] – external edit 127.0.0.1ffc:fpga [2022/09/21 15:23] – external edit 127.0.0.1
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 ====Optical Lock==== ====Optical Lock====
-This tab allows the user to lock and tweak ƒ<sub>opt</sub>: the beatnote between a tooth of the FFC-100 and the reference laser. The process for locking ƒ<sub>opt</sub> is nearly identical to locking ƒ<sub>CEO</sub>, except that there is an extra slider (Offset DAC 2) on the screen. It has no effect on the system, and can be left alone. Begin by adjusting the "Offset DAC 1 [V]" slider until the Baseband IQ is roughly circular, or the beatnote is positioned between two dips on the Spectrum plot corresponding to a band pass filter. Once the beatnote is centered, or the Baseband IQ is roughly circular, check the "Lock" checkbox at the top of the tab and wait a moment. The Phase Noise PSD plot will indicate whether your system is locked by showing a dramatic reduction in noise, and integrated phase noise. If your system is railing, change your VCO sign by selecting the opposite "VCO sign" checkbox to the right of the "Lock" checkbox. To optimize your lock, follow the instructions for adjusting PID settings given in the [[ffc:100m#CEO Lock|CEO Lock section]].+This tab allows the user to lock and tweak ƒ<sub>opt</sub>: the beatnote between a tooth of the FFC-100 and the reference laser. The process for locking ƒ<sub>opt</sub> is nearly identical to locking ƒ<sub>CEO</sub>, except that there is an extra slider (Offset DAC 2) on the screen. It has no effect on the system, and can be left alone. Begin by adjusting the "Offset DAC 1 [V]" slider until the Baseband IQ is roughly circular, or the beatnote is positioned between two dips on the Spectrum plot corresponding to a band pass filter. Once the beatnote is centered, or the Baseband IQ is roughly circular, check the "Lock" checkbox at the top of the tab and wait a moment. The Phase Noise PSD plot will indicate whether your system is locked by showing a dramatic reduction in noise, and integrated phase noise. If your system is railing, change your VCO sign by selecting the opposite "VCO sign" checkbox to the right of the "Lock" checkbox. To optimize your lock, follow the instructions for adjusting PID settings given in the [[ffc:fpga#CEO Lock|CEO Lock section]].
  
 On both the CEO Lock, and Optical Lock tabs, it is possible to change what is being plotted on the Spectrum graph in the Spectrum analyzer/Diagnostics bar. To do so, simply click on the "Plot type:" drop down menu and choose what you would like to plot. The options for this menu are: Spectrum, Time: raw input, Time: phase, Time: IQ, and Time, IQ synced. Choosing any option besides "Spectrum" will change the units on the bottom of the plot from Hz to seconds, and give a live plot of the value selected in the time domain. The same can be done with the Phase noise PSD plot in the Phase noise bar by clicking on the drop down menu in the top left hand corner of the bar (<imgref opt1>). The options for the Phase noise PSD plot are: Frequency (Freq), Phase, and time domain versions of each respectively. Other options for this plot include setting the outer limit for PSD integration scalable X and Y axes, and averaging. When taking a measurement of Phase noise or integrated PSD, it is recommended that the Averaging field be set to no less than 10. On both the CEO Lock, and Optical Lock tabs, it is possible to change what is being plotted on the Spectrum graph in the Spectrum analyzer/Diagnostics bar. To do so, simply click on the "Plot type:" drop down menu and choose what you would like to plot. The options for this menu are: Spectrum, Time: raw input, Time: phase, Time: IQ, and Time, IQ synced. Choosing any option besides "Spectrum" will change the units on the bottom of the plot from Hz to seconds, and give a live plot of the value selected in the time domain. The same can be done with the Phase noise PSD plot in the Phase noise bar by clicking on the drop down menu in the top left hand corner of the bar (<imgref opt1>). The options for the Phase noise PSD plot are: Frequency (Freq), Phase, and time domain versions of each respectively. Other options for this plot include setting the outer limit for PSD integration scalable X and Y axes, and averaging. When taking a measurement of Phase noise or integrated PSD, it is recommended that the Averaging field be set to no less than 10.
ffc/fpga.txt · Last modified: 2022/09/21 16:24 by 127.0.0.1