Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | |
| ffc:fpga [2022/09/21 15:23] – external edit 127.0.0.1 | ffc:fpga [2022/09/21 16:24] (current) – external edit 127.0.0.1 |
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| - Start the SLICE-FPGA control GUI by typing “python XEM_GUI3_VPv4.py”, <imgref gui_start>).\\ <imgcaption gui_start|Start FPGA GUI from Terminal>{{ ffc:terminal_directory.png?800 | ffc:terminal_directory.png}}</imgcaption>\\ | - Start the SLICE-FPGA control GUI by typing “python XEM_GUI3_VPv4.py”, <imgref gui_start>).\\ <imgcaption gui_start|Start FPGA GUI from Terminal>{{ ffc:terminal_directory.png?800 | ffc:terminal_directory.png}}</imgcaption>\\ |
| - A start-up menu should appear (<imgref gui_start_scr>). Make sure “superlaserland_v12.bit” is selected and select an appropriate clock option: internal clock will use the FPGA's on board clock for timing, whereas external clock can be selected to allow synchronization between devices with a separate timing device. If you are unsure which to select, choose Internal Clock. Leave all other settings as default and press OK.\\ <imgcaption gui_start_scr|FPGA GUI Start Screen>{{ ffc:fpga_startup.png?800 | ffc:fpga_startup.png}}</imgcaption>\\ | - A start-up menu should appear (<imgref gui_start_scr>). Make sure “superlaserland_v12.bit” is selected and select an appropriate clock option: internal clock will use the FPGA's on board clock for timing, whereas external clock can be selected to allow synchronization between devices with a separate timing device. If you are unsure which to select, choose Internal Clock. Leave all other settings as default and press OK.\\ <imgcaption gui_start_scr|FPGA GUI Start Screen>{{ ffc:fpga_startup.png?800 | ffc:fpga_startup.png}}</imgcaption>\\ |
| - Navigate to the [[ffc:100m#Filter Settings|Filter Settings]] tab and select “Narrowband (6MHz)” for both DDC0 and DDC1 (<imgref gui_filt>).\\ <imgcaption gui_filt|Set Loop Filter Bandwidth>{{ ffc:fpga_filter_set.png?800 |ffc:fpga_filter_set.png}}</imgcaption>\\ | - Navigate to the [[ffc:fpga#Filter Settings|Filter Settings]] tab and select “Narrowband (6MHz)” for both DDC0 and DDC1 (<imgref gui_filt>).\\ <imgcaption gui_filt|Set Loop Filter Bandwidth>{{ ffc:fpga_filter_set.png?800 |ffc:fpga_filter_set.png}}</imgcaption>\\ |
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| ====CEO Lock==== | ====CEO Lock==== |
