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| ffc:comb_module_quickstart [2022/02/11 17:16] – external edit 127.0.0.1 | ffc:comb_module_quickstart [2022/09/23 16:40] (current) – external edit 127.0.0.1 |
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| ======SVS Fiber Frequency Comb Module Quick Start Guide====== | ======FFC-CM Fiber Frequency Comb Module Quick Start Guide====== |
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| Document Last Updated on ~~LASTMOD~~ | Document Last Updated on ~~LASTMOD~~ |
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| =====Purchase Includes===== | =====Purchase Includes===== |
| * SVS Fiber Frequency Comb Module | * FFC-CM Fiber Frequency Comb Module |
| * Power cord for your country (if known) | * Power cord for your country (if known) |
| * Instructions on how to download & install control software | * Instructions on how to download & install control software |
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| =====Operating the FFC-CM===== | =====Operating the FFC-CM===== |
| This document provides basic instructions on how to operate the Vescent Photonics SVS Fiber Frequency Comb Module in conjunction with the Vescent SLICE-FPGA. It is important to note that the FFC-CM itself does not come with a built in GUI, and as such communication must be done through the [[link|Serial Command API]] or the [[link|FPGA Software]]. This document will walk through usage of the Serial Command interface including several basic commands, as well as using the FPGA Software to obtain and optimize your lock. | This document provides basic instructions on how to operate the Vescent Photonics FFC-CM Fiber Frequency Comb Module in conjunction with the Vescent SLICE-FPGA. It is important to note that the FFC-CM itself does not come with a built in GUI, and as such communication must be done through the [[ffc:cm:api-osc|Serial Command API]] or the [[ffc:comb_module_quickstart #FPGA Control|FPGA Software]]. This document will walk through usage of the Serial Command interface including several basic commands, as well as using the FPGA Software to obtain and optimize your lock. |
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| =====System Set-up===== | =====System Set-up===== |
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| ===Connecting to the Comb Module=== | ===Connecting to the Comb Module=== |
| Once Tera Term is finished installing, launch the application. You will be shown a window like the one in <imgref TT_Open>. Check the "Serial" option and select the COM Port associated with your comb module. To find the correct COM Port, open the Device Manager, and expand the "Ports (COM & LPT)" drop-down. Unplug the USB Type-B to Type-A connector while watching the list of devices. The COM Port of the SVS FFC Module will be the one that disappears and re-appears. Click "OK" in the window. | Once Tera Term is finished installing, launch the application. You will be shown a window like the one in <imgref TT_Open>. Check the "Serial" option and select the COM Port associated with your comb module. To find the correct COM Port, open the Device Manager, and expand the "Ports (COM & LPT)" drop-down. Unplug the USB Type-B to Type-A connector while watching the list of devices. The COM Port of the FFC-CM will be the one that disappears and re-appears. Click "OK" in the window. |
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| <imgcaption TT_Open|Initial Tera Term Window>{{ :ffc:tera_term.png?400 |}}</imgcaption> | <imgcaption TT_Open|Initial Tera Term Window>{{ :ffc:tera_term.png?400 |}}</imgcaption> |
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| <imgcaption Version|Verify that the SVS FFC Module is communicating with the Version command>{{ :ffc:version.png?400 |}}</imgcaption> | <imgcaption Version|Verify that the FFC-CM is communicating with the Version command>{{ :ffc:version.png?400 |}}</imgcaption> |
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| Finally, type ''Version'' into the terminal and hit enter to verify communication with the SVS FFC Module as shown in <imgref Version>. If the connection was successful, the return will be 8 bits showing the firmware version on the SVS FFC Module. | Finally, type ''Version'' into the terminal and hit enter to verify communication with the FFC-CM as shown in <imgref Version>. If the connection was successful, the return will be 8 bits showing the firmware version on the FFC-CM. |
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| ===Sending Commands=== | ===Sending Commands=== |
| With the Serial Command interface set up now, you will be able to send individual commands to the SVS FFC Module by typing them directly into the terminal. During the initial verification and test setup of the SVS FFC Module, it is recommended to use the terminal interface as shown in this guide, though later it may be beneficial to write your own serial command scripts. | With the Serial Command interface set up now, you will be able to send individual commands to the FFC-CM by typing them directly into the terminal. During the initial verification and test setup of the FFC-CM, it is recommended to use the terminal interface as shown in this guide, though later it may be beneficial to write your own serial command scripts. |
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| ====FPGA Control==== | ====FPGA Control==== |
| <imgcaption about|Check whether your operating system is 32-bit or 64-bit>{{ :ffc:about.png?500 |}}</imgcaption> | <imgcaption about|Check whether your operating system is 32-bit or 64-bit>{{ :ffc:about.png?500 |}}</imgcaption> |
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| Open the WinPython folder and navigate to the site-packages directory: ''...\WPy64-3950\python-3.9.5.amd64\Lib\site-packages''. In a new window, also open the FPGA Software folder and locate the file "ok". Copy this file from FPGA Software into the site-packages directory of WinPython. Close the WinPython folder, and open a command line or terminal. Navigate to the ''...\FPGA Software\FPGA Software'' directory in the terminal and run the command ''pip install PyVISA-1.8-py2.py3-none-any.whl''. | Open the WinPython folder and navigate to the site-packages directory: ''...\WPy64-3950\python-3.9.5.amd64\Lib\site-packages''. In a new window, open the FPGA Software folder and locate the file "ok". Copy this file from FPGA Software into the site-packages directory of WinPython. Close the WinPython folder, and open a command line or terminal. Navigate to the ''...\FPGA Software\FPGA Software'' directory in the terminal and run the command ''pip install PyVISA-1.8-py2.py3-none-any.whl''. |
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| <imgcaption pyvisa|A successful installation will look like this. >{{ :ffc:pyvisa_install.png?400 |}}</imgcaption> | <imgcaption pyvisa|A successful installation will look like this. >{{ :ffc:pyvisa_install.png?500 |}}</imgcaption> |
| =====Locking the SVS FFC Module===== | |
| Before locking, it may be beneficial to familiarize yourself with the full list of API commands for the SVS FFC Module, which can be found [[link|here]], as well as the front and rear panel connections, which can be found [[link|here]]. It is also important to note that, aside from those set in the FPGA software, all PID parameters come preset and should not need to be adjusted. | Finally, go back to the FPGA Software folder in your file explorer and run both "FrontPanelUSB-Win-x64-4.5.6", and "vcredist_x64". Each will open their own installer. Follow the instructions on both and click finish. When both are done installing, your computer should be configured to run the FPGA software. |
| | =====Locking the FFC-CM===== |
| | Before locking, it may be beneficial to familiarize yourself with the full list of API commands for the FFC-CM, which can be found [[ffc:cm:api-osc|here]], as well as the front and rear panel connections, which can be found in Figure 8. It is also important to note that, aside from those set in the FPGA software, all PID parameters come preset and should not need to be adjusted. |
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| ===Connections=== | ===Connections=== |
| After initial verification of the SVS FFC Module with Tera Term, the system as a whole can be connected as shown in <imgref Diagram>. The USB "Optional Programming Interface" labeled "13" should already be connected to a Windows 10 machine, and should be left connected for the duration of this setup. Ensure that the FPGA remains off until [[ffc:comb_module_quickstart#Step 7: Power on and Set Up the FPGA|Step 7]]. In general, do not power on any components of the system until explicitly instructed to do so. Failing to follow the correct start-up order may damage your system. | After initial verification of the FFC-CM with Tera Term, the system as a whole can be connected as shown in <imgref Diagram>. The USB "Optional Programming Interface" labeled "13" should already be connected to a Windows 10 machine, and should be left connected for the duration of this setup. Ensure that the FPGA remains off until [[ffc:comb_module_quickstart#Step 7: Power on and Set Up the FPGA|Step 7]]. In general, do not power on any components of the system until explicitly instructed to do so. Failing to follow the correct start-up order may damage your system. |
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| <imgcaption Diagram|High Level Block Diagram of SVS FFC Module system>{{ :ffc:high_level_diagram.png?600 |}}</imgcaption> | <imgcaption Diagram|High Level Block Diagram of FFC-CM system>{{ :ffc:high_level_diagram.png?600 |}}</imgcaption> |
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| ===Step 2: Power Pump Diode Boards=== | ===Step 2: Power Pump Diode Boards=== |
| The actual I<sup>2</sup>C implementation of the Pump Diode boards has been left to the user, but in general it is at this time that the pump diode boards should be powered on and temperature stabilized. Do **not** supply current to the diodes themselves until their temperature has stabilized. If connections have not been made already, ensure that the OSC Out (Pump 1) and any EDFA Amplifiers (Pumps 2 and 3) on the Pump Diode Board have been connected to the SVS FFC Module as shown in <imgref Diagram>. | The actual I<sup>2</sup>C implementation of the Pump Diode boards has been left to the user, but in general it is at this time that the pump diode boards should be powered on and temperature stabilized. Do **not** supply current to the diodes themselves until their temperature has stabilized. If connections have not been made already, ensure that the OSC Out (Pump 1) and any EDFA Amplifiers (Pumps 2 and 3) on the Pump Diode Board have been connected to the FFC-CM as shown in <imgref Diagram>. |
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| ===Step 3: Power and Connect CW Laser=== | ===Step 3: Power and Connect CW Laser=== |
| It is essential that the SVS FFC Module be locked to an external reference, which should now be powered on and connected to the SVS FFC Module if it was not connected already. Follow the start-up procedure for your given CW reference laser. | It is essential that the FFC-CM be locked to an external reference, which should now be powered on and connected to the FFC-CM if it was not connected already. Follow the start-up procedure for your given CW reference laser. |
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| Wrap this: | Wrap this: |
| The maximum power input for CW in is 2mW. Exceeding this input power may damage your system. | The maximum power input for CW in is 2mW. Exceeding this input power may damage your system. |
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| ===Step 4: Mode Lock the SVS FFC Module=== | ===Step 4: Mode Lock the FFC-CM=== |
| Connect the OSC Mon output to a spectrum analyzer or OSA. Check that the OSC pump diode's current setting is within the specified range of your CoC, and then enable current to the OSC pump. It is recommended to start near the middle of the specified current range, and then to increase the current until CW breakthrough can be observed on the spectrum in the form of a narrow peak forming above the broader curve. Once CW breakthrough is achieved, lower the current roughly 10 mA to give the system room to modulate for a lock. | Connect the OSC Mon output to a spectrum analyzer or OSA. Check that the OSC pump diode's current setting is within the specified range of your CoC, and then enable current to the OSC pump. It is recommended to start near the middle of the specified current range, and then to increase the current until CW breakthrough can be observed on the spectrum in the form of a narrow peak forming above the broader curve. Once CW breakthrough is achieved, lower the current roughly 10 mA to give the system room to modulate for a lock. |
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| ===Step 5: Verify Supercontinuum=== | ===Step 5: Verify Supercontinuum=== |
| Now that the system is mode locked, switch the monitored output to SC Out and change your Spectrum Analyzer or OSA's window to span the 1-2 micron wavelength region. Verify that the supercontinuum of your system matches that shown in your CoC. An example supercontinuum can be seen in <imgref SC> | Now that the system is mode locked, turn on the EDFA/AMP pump diode and switch the monitored output to SC Out. Change your Spectrum Analyzer or OSA's window to span the 1-2 micron wavelength region and verify that the supercontinuum of your system matches that shown in your CoC. An example supercontinuum can be seen in <imgref SC> |
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| <imgcaption SC|Example supercontinuum of the SVS FCC Module system>{{ :ffc:boeingffc_system1_scout.png?400 |}}</imgcaption> | <imgcaption SC|Example supercontinuum of the FCC-CM system>{{ :ffc:boeingffc_system1_scout.png?400 |}}</imgcaption> |
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| ===Step 6: Verify RF Output=== | ===Step 6: Verify RF Output=== |
| Connect the RF Mon output to a spectrum analyzer to verify that the RF output matches what is shown in your CoC. Set the spectrum analyzer's span to 1kHz-2GHz and look for a series of equally spaced peaks as shown in <imgref RF>. The first peak is the repetition rate of your SVS FFC Module, and the rest are harmonics. | Connect the RF Mon output to a spectrum analyzer to verify that the RF output matches what is shown in your CoC. Set the spectrum analyzer's span to 1kHz-2GHz and look for a series of equally spaced peaks as shown in <imgref RF>. The first peak is the repetition rate of your FFC-CM, and the rest are harmonics. |
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| <imgcaption RF|Example RF spectrum from the SVS FFC Module system with 100 MHz repetition rate>{{ :ffc:boeingffc_system1_freprfspec.png?400 |}}</imgcaption> | <imgcaption RF|Example RF spectrum from the FFC-CM system with 100 MHz repetition rate>{{ :ffc:boeingffc_system1_freprfspec.png?400 |}}</imgcaption> |
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| ===Step 7: Power On and Set Up the FPGA=== | ===Step 7: Power On and Set Up the FPGA=== |
| After verifying the outputs of the SVS FFC Module, make connections to the FPGA as shown in <imgref Diagram> if they have not been made already, and turn the FPGA on. The FPGA will apply a modulation current to the oscillator, which if not accounted for properly in [[:ffc:comb_module_quickstart#Step 4: Mode Lock the SVS FFC Module|Step 4]] may cause your system to leave its mode lock regime. Open a WinPython terminal and navigate to the ''...\"FPGA Software"\"GUI and Firmware"'' folder then run ''python XEM_GUI3_VPv4.py'' to launch the FPGA software. A window will appear asking for initial configuration settings as shown in <imgref startup>. Ensure that "superlaserland_v12.bit" is selected for Fimware File, and check the "Send Firmware" and "Internal Clock (100 MHz)" boxes. | After verifying the outputs of the FFC-CM, make connections to the FPGA as shown in <imgref Diagram> if they have not been made already, and turn the FPGA on. The FPGA will apply a modulation current to the oscillator, which if not accounted for properly in [[:ffc:comb_module_quickstart#Step 4: Mode Lock the FFC-CM|Step 4]] may cause your system to leave its mode lock regime. Open a WinPython terminal and navigate to the ''...\"FPGA Software"\"GUI and Firmware"'' folder then run ''python XEM_GUI3_VPv4.py'' to launch the FPGA software. A window will appear asking for initial configuration settings as shown in <imgref startup>. Ensure that "superlaserland_v12.bit" is selected for Fimware File, and check the "Send Firmware" and "Internal Clock (100 MHz)" boxes. |
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| <imgcaption startup|Configuration window shown before FPGA software launches>{{ :ffc:fpga_startup.png?600 |}}</imgcaption> | <imgcaption startup|Configuration window shown before FPGA software launches>{{ :ffc:fpga_startup.png?600 |}}</imgcaption> |
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| ===Step 8: CEO Lock=== | ===Step 8: CEO Lock=== |
| Begin by navigating to the CEO Lock tab, then ensure that there is a visible beatnote displayed on the “Spectrum” plot. This will be an obvious peak above the noise floor which responds to adjustments of the “Offset DAC 0 [V]” slider as shown in <imgref CEO_1>. If a beatnote cannot be identified, check that the SVS FFC Module is still mode locked. Once a beatnote has been identified, adjust the “Offset DAC 0 [V]” slider such that the Baseband IQ plot is roughly circular, or the identified beatnote is between two of the dips on the spectrum plot corresponding to a bandpass filter. | Begin by navigating to the CEO Lock tab, then ensure that there is a visible beatnote displayed on the “Spectrum” plot. This will be an obvious peak above the noise floor which responds to adjustments of the “Offset DAC 0 [V]” slider as shown in <imgref CEO_1>. If a beatnote cannot be identified, check that the FFC-CM is still mode locked. Once a beatnote has been identified, adjust the “Offset DAC 0 [V]” slider such that the Baseband IQ plot is roughly circular, or the identified beatnote is between two of the dips on the spectrum plot corresponding to a bandpass filter. |
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| <imgcaption CEO_1|Offset DAC location and Beatnote Example>{{ :ffc:ceo_lock_pt_1.png?600 |}}</imgcaption> | <imgcaption CEO_1|Offset DAC location and Beatnote Example>{{ :ffc:ceo_lock_pt_1.png?600 |}}</imgcaption> |
| - The PZT setpoint is set to an intermediate value (50V) to keep the servo from railing. This can be adjusted if desired. | - The PZT setpoint is set to an intermediate value (50V) to keep the servo from railing. This can be adjusted if desired. |
| - Click “Activate Temperature Slow Loop”. | - Click “Activate Temperature Slow Loop”. |
| guide. | |
