| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| ffc:cm:quickstart [2021/12/09 17:24] – external edit 127.0.0.1 | ffc:cm:quickstart [2021/12/14 18:23] (current) – external edit 127.0.0.1 |
|---|
| </WRAP> | </WRAP> |
| |
| If satisfied that the output power of the pump diodes is safe, ensure that the pump fiber ends are clean using a fiber cleaner, then connect the OSC Out (Pump 1) and any EDFA Amplifiers (Pumps 2 and 3) on the Pump Diode Board to the FFC-CM as shown in <imgref Diagram>. If you're using the 1556nm system, there will only be one amplifier pump diode. If you're using the 778nm system, there will be two amplifier pump diodes. | If satisfied that the output power of the pump diodes is safe, ensure that the pump fiber ends are clean using a fiber cleaner, then connect the oscillator pump and amplifier pump(s) on the Pump Diode Board to the FFC-CM as shown in <imgref Diagram>. If you're using the 1556nm system, there will only be one amplifier pump diode. If you're using the 778nm system, there will be two amplifier pump diodes. |
| |
| ===Step 3: Power and Connect CW Laser=== | ===Step 3: Power and Connect CW Laser=== |
| <imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> | <imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> |
| |
| Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from //f<sub>CEO</sub>'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of //f<sub>CEO</sub>// is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. | Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from //f<sub>CEO</sub>//'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of //f<sub>CEO</sub>// is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. |
| |
| <imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> | <imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> |
| |
| |
| <imgcaption Optical_PhaseNoise|//f_OPT// Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> | <imgcaption Optical_PhaseNoise|f_OPT Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> |
| |
| ====Optimizing FPGA PID Locking Parameters==== | ====Optimizing FPGA PID Locking Parameters==== |
