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| ffc:cm:quickstart [2021/12/09 16:58] – external edit 127.0.0.1 | ffc:cm:quickstart [2021/12/14 18:23] (current) – external edit 127.0.0.1 |
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| A labeled diagram of the rear panel is shown in <imgref rear>. The functions and connections are as follows: | A labeled diagram of the rear panel is shown in <imgref rear>. The functions and connections are as follows: |
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| - Mini USB Serial Communication Port | - Mini USB Serial Communication Port (accepts API commands) |
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| ====FPGA Control==== | ====FPGA Control==== |
| The SLICE-FPGA dual-channel Offset Phase Lock Servo can be used to phase lock ƒ<sub>CEO</sub> and ƒ<sub>opt</sub>. Locking f<sub>opt</sub> requires a reference CW laser. The stability of the lock will depend on the reference laser used. All performance data generated at Vescent is collected using a 1556.2 nm Rio Planex Laser as the CW reference laser. | The SLICE-FPGA dual-channel Offset Phase Lock Servo can be used to phase lock //ƒ<sub>CEO</sub>// and //ƒ<sub>OPT</sub>//. Locking //f<sub>OPT</sub>// requires a reference CW laser. The stability of the lock will depend on the reference laser used. All performance data generated at Vescent is collected using a 1556.2 nm Rio Planex Laser as the CW reference laser. |
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| ===Installing FPGA Software=== | ===Installing FPGA Software=== |
| </WRAP> | </WRAP> |
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| If satisfied that the output power of the pump diodes is safe, ensure that the pump fiber ends are clean using a fiber cleaner, then connect the OSC Out (Pump 1) and any EDFA Amplifiers (Pumps 2 and 3) on the Pump Diode Board to the FFC-CM as shown in <imgref Diagram>. If you're using the 1556nm system, there will only be one amplifier pump diode. If you're using the 778nm system, there will be two amplifier pump diodes. | If satisfied that the output power of the pump diodes is safe, ensure that the pump fiber ends are clean using a fiber cleaner, then connect the oscillator pump and amplifier pump(s) on the Pump Diode Board to the FFC-CM as shown in <imgref Diagram>. If you're using the 1556nm system, there will only be one amplifier pump diode. If you're using the 778nm system, there will be two amplifier pump diodes. |
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| ===Step 3: Power and Connect CW Laser=== | ===Step 3: Power and Connect CW Laser=== |
| <imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> | <imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> |
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| Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from ƒCEO's unlocked state. This number is a good characterization of the stability of your lock. A good lock of ƒCEO is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. | Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from //f<sub>CEO</sub>//'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of //f<sub>CEO</sub>// is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. |
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| <imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> | <imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> |
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| After obtaining a lock, it is possible to change the lock frequency using the "Reference freq [Hz]:" field in the FPGA GUI. To do so, unlock f<sub>CEO</sub>, then change the value of "Reference freq [Hz]:" and relock the FFC-CM. If you do not unlock the laser first, you will likely rail the modulation output. | After obtaining a lock, it is possible to change the lock frequency using the "Reference freq [Hz]:" field in the FPGA GUI. To do so, unlock //f<sub>CEO</sub>//, then change the value of "Reference freq [Hz]:" and relock the FFC-CM. If you do not unlock the laser first, you will likely rail the modulation output. |
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| <imgcaption ref_freq|Location of the "Reference freq [Hz]:" field>{{ :ffc:cm:ceo_lock_pt_5.png?600 |}}</imgcaption> | <imgcaption ref_freq|Location of the "Reference freq [Hz]:" field>{{ :ffc:cm:ceo_lock_pt_5.png?600 |}}</imgcaption> |
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| ===Step 9: Optical Lock=== | ===Step 9: Optical Lock=== |
| The process for locking ƒ<sub>opt</sub> is nearly identical to locking ƒ<sub>CEO</sub>, except that there is an extra slider (Offset DAC 2) on the screen. It has no effect on the system, and can be left alone. Begin by adjusting the "Offset DAC 1 [V]" slider until the beatnote is centered within the red bandpass filter spectrum. Check for the VCO sign by adjusting the "Offset DAC 1 [V]" slider as described in [[ffc:cm:quickstart#Step 8: CEO Lock|Step 8]], check the appropriate VCO sign box, then check the "Lock" checkbox at the top of the tab and wait a moment. The Phase Noise PSD plot will indicate whether your system is locked by showing a dramatic reduction in noise, and standard deviation. If your system is railing, change your VCO sign by selecting the opposite "VCO sign" checkbox to the right of the "Lock" checkbox. To optimize your lock, follow the instructions for [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. As with f<sub>CEO</sub>, the lock frequency can be changed using the "Reference freq [Hz]:" field in the FPGA GUI. Once again, this should be done while the system is unlocked. | The process for locking //ƒ<sub>OPT</sub>// is nearly identical to locking //f<sub>CEO</sub>//, except that there is an extra slider (Offset DAC 2) on the screen. It has no effect on the system, and can be left alone. Begin by adjusting the "Offset DAC 1 [V]" slider until the beatnote is centered within the red bandpass filter spectrum. Check for the VCO sign by adjusting the "Offset DAC 1 [V]" slider as described in [[ffc:cm:quickstart#Step 8: CEO Lock|Step 8]], check the appropriate VCO sign box, then check the "Lock" checkbox at the top of the tab and wait a moment. The Phase Noise PSD plot will indicate whether your system is locked by showing a dramatic reduction in noise, and standard deviation. If your system is railing, change your VCO sign by selecting the opposite "VCO sign" checkbox to the right of the "Lock" checkbox. To optimize your lock, follow the instructions for [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. As with //f<sub>CEO</sub>//, the lock frequency can be changed using the "Reference freq [Hz]:" field in the FPGA GUI. Once again, this should be done while the system is unlocked. |
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| <imgcaption Optical_PhaseNoise|f_opt Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> | <imgcaption Optical_PhaseNoise|f_OPT Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> |
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| ====Optimizing FPGA PID Locking Parameters==== | ====Optimizing FPGA PID Locking Parameters==== |
