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ffc:cm:quickstart [2021/12/09 17:24] – external edit 127.0.0.1 | ffc:cm:quickstart [2021/12/09 17:27] – external edit 127.0.0.1 |
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<imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> | <imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption> |
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Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from //f<sub>CEO</sub>'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of //f<sub>CEO</sub>// is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. | Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from //f<sub>CEO</sub>//'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of //f<sub>CEO</sub>// is indicated by a std_dev less than 2 rad, but this value can be pushed down even further by [[ffc:cm:quickstart#Optimizing FPGA PID Locking Parameters|optimizing the PID settings]] of the FFC-CM. |
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<imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> | <imgcaption CEO_PhaseNoise|f_CEO Phase Noise Example>{{ :ffc:cm:boeingffc_system1_fceophasenoise.png?400 |}}</imgcaption> |
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<imgcaption Optical_PhaseNoise|//f_OPT// Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> | <imgcaption Optical_PhaseNoise|f_OPT Phase Noise Example>{{ :ffc:cm:boeingffc_system1_foptphasenoise.png?400 |}}</imgcaption> |
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====Optimizing FPGA PID Locking Parameters==== | ====Optimizing FPGA PID Locking Parameters==== |