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| ffc:100m [2022/09/21 16:14] – external edit 127.0.0.1 | ffc:100m [2023/11/30 21:32] (current) – external edit 127.0.0.1 |
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| Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the FFC-100. | Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the FFC-100. |
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| {{ffc:ffc-100_class_iiib.png?&200}} | {{ffc:ffc-100_class_iiib.png&200}} |
| <imgcaption ffc|The FFC-100 Fiber Frequency Comb>{{ 210226_ffc_front_210_kb.png?350|}}</imgcaption> | <imgcaption ffc|The FFC-100 Fiber Frequency Comb>{{ ffc_front_250_kb.png?350|}}</imgcaption> |
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| ====Links==== | ====Links==== |
| Click here for the [[https://sourceforge.net/projects/winpython/|latest version of WinPython]]\\ | Click here for the [[https://sourceforge.net/projects/winpython/|latest version of WinPython]]\\ |
| Click here for the [[https://github.com/Vescent/SLICE-FFC_Firmware_Upgrade_Utility|Github page for FFC-100 Upgrade Utility]]\\ | Click here for the [[https://github.com/Vescent/SLICE-FFC_Firmware_Upgrade_Utility|Github page for FFC-100 Upgrade Utility]]\\ |
| Click here for the [[ffc:locking_electronics:rpm-100|RPM-100 FPGA Locking Manual]]\\ | Click here for the [[ffc:fpga|SLICE-FPGA Locking Manual]]\\ |
| | Click here for the [[ffc:locking_electronics:slice-fpga-ii|SLICE-FPGA-II Locking Manual]] |
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| =====Specifications===== | =====Specifications===== |
| <WRAP center round box 60%><tabcaption specs|Specifications of FFC-100> | <WRAP center round box 60%><tabcaption specs|Specifications of FFC-100> |
| | **Performance((Subject to change without notice))** |||| | | **Performance((Subject to change without notice))** |||| |
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| ^ Parameter ^^ Value ^^ | ^ Parameter ^^ Value ^^ |
| | ƒ<sub>opt</sub> Locked Phase Noise || <500 mrad|| | | ƒ<sub>opt</sub> Locked Phase Noise || <200 mrad|| |
| | ƒ<sub>CEO</sub> Locked Phase Noise || <3 rad|| | | ƒ<sub>CEO</sub> Locked Phase Noise || <3 rad|| |
| | In-Loop Allan Deviations || <10<sup>-17</sup>|| | | In-Loop Allan Deviations || <10<sup>-17</sup>|| |
| | **Optical IO** |||| | | **Optical IO** |||| |
| ||||| | ^ Input / Output ^^ Power ^^ |
| ^ Input / Output ^ Type ^ Current ^ Power ^ | | OSC Out || 130 µW || |
| | OSC Out | PM FC/APC | 225-445 mA ((CW-breakthrough occurs at currents above 445 mA)) | 130 µW | | | EDFA Out || 8.8 mW || |
| | EDFA Out | PM FC/APC | 1575 mA ((current setting of the AMP pump diode)) | 8.8 mW | | | SC Out || >50 mW || |
| | SC Out | PM FC/APC | 1575 mA ((current setting of the AMP pump diode)) | >50 mW | | | ƒ<sub>opt</sub> In || < 1.5mW maximum || |
| | ƒ<sub>opt</sub> In | PM FC/APC | -- | < 1.5mW maximum | | |
| | **RF IO** |||| | | **RF IO** |||| |
| ||||| | ||||| |
| ^ Input / Output ^ Type ^^ Output ^ | ^ Input / Output ^ Type ^^ Output ^ |
| | ƒ<sub>rep</sub> MON | SMA || >-3 dBm at rep rate ((100 MHz, 125 MHz, or 200 MHz depending on model)) of comb| | | ƒ<sub>rep</sub> MON | SMA || >-3 dBm at rep rate ((100 MHz, or 200 MHz depending on model)) of comb| |
| | ƒ<sub>opt</sub> MON | SMA || >-10 dBm, >50 dB SNR beat note between comb and optical input| | | ƒ<sub>opt</sub> MON | SMA || >-10 dBm, >50 dB SNR beat note between comb and optical input| |
| | ƒ<sub>CEO</sub> MON | SMA || >-30 dBm, >30 dB SNR beat note inherent to self-referenced frequency comb| | | ƒ<sub>CEO</sub> MON | SMA || >-30 dBm, >30 dB SNR beat note inherent to self-referenced frequency comb| |
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| </tabcaption></WRAP> | </tabcaption></WRAP> |
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| =====Features===== | =====Features===== |
| <imgcaption FCEO|f_CEO Beatnote>{{ :ffc:fceo_beatnote.png?400 |}}</imgcaption> | <imgcaption FCEO|f_CEO Beatnote>{{ :ffc:fceo_beatnote.png?400 |}}</imgcaption> |
| =====FPGA Control===== | =====FPGA Control===== |
| For locking the FFC-100 with the Vescent RPM-100 Module, [[ffc:locking_electronics:rpm-100|click here]]. Otherwise, if using the SLICE-FPGA, [[ffc:fpga|click here]]. | For locking the FFC-100 with the Vescent SLICE-FPGA-II Module, [[ffc:locking_electronics:slice-fpga-ii|click here]]. Otherwise, if using the SLICE-FPGA, [[ffc:fpga|click here]]. |
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| ====Dither==== | |
| The Dither tab allows the user to add a modulation to the DAC current. Each DAC can individually be configured to be modulated at a specific frequency, integration time, and amplitude. A checkbox below these fields allows the user to select whether the modulation is always on (Manual On), always off (Manual Off), or to allow the computer to determine when the modulation is applied (Automatic). | |
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| ====Slow Loop==== | =====Slow Loop===== |
| ===Firmware Version FL-V1.2=== | ===Firmware Version FL-V1.2=== |
| The Slow Loop tab allows the user to enable a slow servo temperature control of the intracavity PZT to prevent offset drift over long periods of time. It is recommended to always enable this feature after setting up a lock, as without it the PZT's offset voltage can drift to its rails over the course of several hours or even less. To enable the Slow Loop feature, simply fill in the "FFC COM Port:" field with the number corresponding to your FFC-100's COM port, choose the desired setpoint of the PZT, and press the "Activate Temperature Slow Loop" button at the top of the tab. For example, if your FPGA is on COM4, and your FFC-100 is on COM8, type "8" into the "FFC Com Port:" field and then press the button. This will bring up a command prompt window which will display information about the Slow Loop, such as the cavity temperature, and the current PZT setpoint. In general, it is best to select a setpoint near the center of the PZT's available range. | The Slow Loop tab of either the the SLICE-FPGA allows the user to enable a slow servo temperature control of the intracavity PZT to prevent offset drift over long periods of time. It is recommended to always enable this feature after setting up a lock, as without it the PZT's offset voltage can drift to its rails over the course of several hours or even less. To enable the Slow Loop feature, simply fill in the "FFC COM Port:" field with the number corresponding to your FFC-100's COM port, choose the desired setpoint of the PZT, and press the "Activate Temperature Slow Loop" button at the top of the tab. For example, if your FPGA is on COM4, and your FFC-100 is on COM8, type "8" into the "FFC Com Port:" field and then press the button. This will bring up a command prompt window which will display information about the Slow Loop, such as the cavity temperature, and the current PZT setpoint. In general, it is best to select a setpoint near the center of the PZT's available range. |
| <WRAP center round important 100%>To determine the COM port of your FFC, open the Windows Device Manager on your PC, expand the "Ports (COM & LPT)" drop down, take note of which COM ports are listed, then unplug the FFC-100's USB connection. After the list updates, the COM port of the FFC-100 will no longer be listed. | <WRAP center round important 100%>To determine the COM port of your FFC-100, open the Windows Device Manager on your PC, expand the "Ports (COM & LPT)" drop down, take note of which COM ports are listed, then unplug the FFC-100's USB connection. After the list updates, the COM port of the FFC-100 will no longer be listed. |
| </WRAP> | </WRAP> |
| ===Firmware Version G2-V1.2=== | ===Firmware Version G2-V1.2=== |
