Differences

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--- ffc:100m [2022/09/21 15:40] – external edit 127.0.0.1
+++ ffc:100m [2023/11/30 21:32] (current) – external edit 127.0.0.1
@@ Line 6: / Line 6: @@
 Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the FFC-100.
-{{ffc:ffc-100_class_iiib.png?&200}}
+{{ffc:ffc-100_class_iiib.png&200}}
-<imgcaption ffc|The FFC-100 Fiber Frequency Comb>{{ 210226_ffc_front_210_kb.png?350|}}</imgcaption>
+<imgcaption ffc|The FFC-100 Fiber Frequency Comb>{{ ffc_front_250_kb.png?350|}}</imgcaption>
 ====Links====
@@ Line 18: / Line 18: @@
 Click here for the  [[https://sourceforge.net/projects/winpython/|latest version of WinPython]]\\
 Click here for the [[https://github.com/Vescent/SLICE-FFC_Firmware_Upgrade_Utility|Github page for FFC-100 Upgrade Utility]]\\
-Click here for the [[ffc:locking_electronics:rpm-100|RPM-100 FPGA Locking Manual]]\\
+Click here for the [[ffc:fpga|SLICE-FPGA Locking Manual]]\\
+Click here for the [[ffc:locking_electronics:slice-fpga-ii|SLICE-FPGA-II Locking Manual]]
@@ Line 107: / Line 108: @@
 =====Specifications=====
 <WRAP center round box 60%><tabcaption specs|Specifications of FFC-100>
 |  **Performance((Subject to change without notice))**   ||||
-|||||
 ^  Parameter  ^^  Value  ^^
-| ƒ<sub>opt</sub> Locked Phase Noise || <500 mrad||
+| ƒ<sub>opt</sub> Locked Phase Noise || <200 mrad||
 | ƒ<sub>CEO</sub> Locked Phase Noise || <3 rad||
 | In-Loop Allan Deviations || <10<sup>-17</sup>||
 | **Optical IO** ||||
-|||||
+^  Input / Output   ^^  Power  ^^
-^  Input / Output  ^  Type  ^  Current  ^  Power  ^
+| OSC Out || 130 µW ||
-| OSC Out | PM FC/APC | 225-445 mA ((CW-breakthrough occurs at currents above 445 mA)) | 130 µW |
+| EDFA Out || 8.8 mW ||
-| EDFA Out | PM FC/APC | 1575 mA ((current setting of the AMP pump diode)) | 8.8 mW |
+| SC Out || >50 mW ||
-| SC Out | PM FC/APC | 1575 mA ((current setting of the AMP pump diode)) | >50 mW |
+| ƒ<sub>opt</sub> In || < 1.5mW maximum ||
-| ƒ<sub>opt</sub> In | PM FC/APC | -- | < 1.5mW maximum |
 | **RF IO** ||||
 |||||
 ^  Input / Output  ^  Type  ^^  Output  ^
-| ƒ<sub>rep</sub> MON | SMA || >-3 dBm at rep rate ((100 MHz, 125 MHz, or 200 MHz depending on model)) of comb|
+| ƒ<sub>rep</sub> MON | SMA || >-3 dBm at rep rate ((100 MHz, or 200 MHz depending on model)) of comb|
 | ƒ<sub>opt</sub> MON | SMA || >-10 dBm, >50 dB SNR beat note between comb and optical input|
 | ƒ<sub>CEO</sub> MON | SMA || >-30 dBm, >30 dB SNR beat note inherent to self-referenced frequency comb|
 |||||
 </tabcaption></WRAP>
 =====Features=====
@@ Line 332: / Line 330: @@
-<imgcaption FCEO|f(CEO) Beatnote{{ :ffc:fceo_beatnote.png?400 |}}</imgcaption>
+<imgcaption FCEO|f_CEO Beatnote>{{ :ffc:fceo_beatnote.png?400 |}}</imgcaption>
 =====FPGA Control=====
-For locking the FFC-100 with the Vescent RPM-100 Module, [[ffc:locking_electronics:rpm-100|click here]]. Otherwise, if using the SLICE-FPGA, [[ffc:fpga|click here]].
+For locking the FFC-100 with the Vescent SLICE-FPGA-II Module, [[ffc:locking_electronics:slice-fpga-ii|click here]]. Otherwise, if using the SLICE-FPGA, [[ffc:fpga|click here]].
-====CEO Lock====
-This tab of the FPGA software allows the user to lock ƒ<sub>CEO</sub>, and to tweak the parameters of the lock for best performance. To lock ƒ<sub>CEO</sub>, first ensure that there is a visible beatnote displayed on the "Spectrum" plot. This will be an obvious peak above the noise floor which responds to adjustments of the "Offset DAC 0 [V]" slider. If a beatnote cannot be identified, check that the FFC-100 is mode locked.  Once a beatnote has been identified, adjust the "Offset DAC 0 [V]" slider such that the [[https://en.wikipedia.org/wiki/In-phase_and_quadrature_components|Baseband IQ]] plot is roughly circular, or the identified beatnote is between two of the dips on the spectrum plot corresponding to a bandpass filter (<imgref pt1>). It is important to note that, while the "Offset DAC 0 [V]" slider range displays values between 0 and 8V, the DAC itself is incapable of going higher than 4V, so make sure that the slider is between 0V and 4V while making this adjustment. If the slider is placed higher than 4V it will not damage the system, but it might cause problems with obtaining a lock.
-\\ <imgcaption pt1| Offset DAC location and Beatnote Example>{{ :ffc:ceo_lock_pt_1.png?600 |ffc:ceo_lock_pt_1.png}}</imgcaption>\\
-To lock the system, simply click the checkbox at the top of the screen labeled "Lock" and the system should snap fairly quickly into a lock. If the system does not lock, and immediately rails, uncheck the "Lock" checkbox, change the sign of the VCO by selecting the opposite "VCO sign" checkbox to the right of the "lock" checkbox, and try again. If the system still does not lock, check that your PID parameters are set to, or near to, the values given in your CoC and shipped with the system. If there is still no lock, check the [[ffc:100m#Troubleshooting/Common Issues|Troubleshooting]] section for potential solutions.
-\\ <imgcaption pt1| Offset DAC location and Beatnote Example>{{ :ffc:ceo_lock_pt_2.png?600 |ffc:ceo_lock_pt_2.png}}</imgcaption>\\
-Once a lock has been obtained, the green plot of phase noise on the "Phase Noise PSD, std dev =" plot will show a dramatic reduction in noise from ƒ<sub>CEO</sub>'s unlocked state. This number is a good characterization of the stability of your lock. A good lock of ƒ<sub>CEO</sub> is indicated by an integrated phase noise PSD less than 2 rad, but this value can be pushed down even further by adjusting the PID settings of your FFC-100.
-Before adjusting the PID parameters, uncheck "Auto-refresh" at the top of the screen. Change the value of "RBW: 576 Hz; Points:" to  "3e6", then recheck "Auto-refresh" (<imgref pt3>). This will update the graph to plot more points and give a more accurate representation of the phase noise. It is important that Auto-Refresh be unchecked before making this adjustment, however, as doing so while the plot is refreshing may cause the FPGA software to crash. If this happens, simply relaunch the software and start again.
-<imgcaption pt3|Resetting the RBW and Plot Points to get more accurate phase noise plot>{{ :ffc:ceo_lock_pt_3.png?600 |ffc:ceo_lock_pt_3.png}}</imgcaption>
-The PID settings provided with the FFC-100 on delivery are intended to give a relatively stable lock out of the box in normal laboratory conditions. If at any point the PID parameters are adjusted too far out of range and the FFC-100 is not locking, resetting them to ship parameters will allow you to quickly get back to a baseline lock. The PID parameters shipped with the FFC-100 can be found in section 6 of CoC delivered with your FFC-100.
-Adjustment of the PID settings to obtain a tighter lock can be done from the bottom section on the CEO lock tab (<imgref pt4>). Begin by resetting the parameters to ship settings, and then adjust Kp by clicking on its slider, then pressing the arrow keys on your keyboard. It is possible to move the slider with the mouse, or by typing in a value, but the keyboard arrow keys will provide the most fine tuned control of the value. Change the value up or down and watch the number displayed in the Phase Noise PSD plot to ensure that the changes are reducing integrated phase noise. After optimizing Kp, if the integrated phase noise is still too high, go through the other PID parameter sliders underneath until you have reached your desired noise optimization. In general, small adjustments of Kp will provide the largest change in integrated phase noise, assuming that all values begin close to ideal.
-<imgcaption pt4|PID Control sliders>{{ :ffc:ceo_lock_pt_4.png?600 |ceo_lock_pt_4.png}}</imgcaption>
-====Optical Lock====
-This tab allows the user to lock and tweak ƒ<sub>opt</sub>: the beatnote between a tooth of the FFC-100 and the reference laser. The process for locking ƒ<sub>opt</sub> is nearly identical to locking ƒ<sub>CEO</sub>, except that there is an extra slider (Offset DAC 2) on the screen. It has no effect on the system, and can be left alone. Begin by adjusting the "Offset DAC 1 [V]" slider until the Baseband IQ is roughly circular, or the beatnote is positioned between two dips on the Spectrum plot corresponding to a band pass filter. Once the beatnote is centered, or the Baseband IQ is roughly circular, check the "Lock" checkbox at the top of the tab and wait a moment. The Phase Noise PSD plot will indicate whether your system is locked by showing a dramatic reduction in noise, and integrated phase noise. If your system is railing, change your VCO sign by selecting the opposite "VCO sign" checkbox to the right of the "Lock" checkbox. To optimize your lock, follow the instructions for adjusting PID settings given in the [[ffc:100m#CEO Lock|CEO Lock section]].
-On both the CEO Lock, and Optical Lock tabs, it is possible to change what is being plotted on the Spectrum graph in the Spectrum analyzer/Diagnostics bar. To do so, simply click on the "Plot type:" drop down menu and choose what you would like to plot. The options for this menu are: Spectrum, Time: raw input, Time: phase, Time: IQ, and Time, IQ synced. Choosing any option besides "Spectrum" will change the units on the bottom of the plot from Hz to seconds, and give a live plot of the value selected in the time domain. The same can be done with the Phase noise PSD plot in the Phase noise bar by clicking on the drop down menu in the top left hand corner of the bar (<imgref opt1>). The options for the Phase noise PSD plot are: Frequency (Freq), Phase, and time domain versions of each respectively. Other options for this plot include setting the outer limit for PSD integration scalable X and Y axes, and averaging. When taking a measurement of Phase noise or integrated PSD, it is recommended that the Averaging field be set to no less than 10.
-<imgcaption opt1| Several options are available for how the Phase noise PSD plot is displayed.>{{ :ffc:opt_pt_1.png?600 |}}</imgcaption>
-To export data from the FPGA to a file, simply press one of the two export buttons in the Settings bar at the top of the tab(<imgref opt2>). If ADC data is being exported, a pop-up will appear and ask the user which ADC to export. The files will be saved in csv format to the Software and GUI folder from which the FPGA software is launched under data_exports. If this folder does not exist in that location, it will be created the first time data is exported.
-<imgcaption opt2|Export ADC data, or the Phase noise PSD chart to CSV>{{ :ffc:opt_pt_2.png?600 |ffc:opt_pt_2.png}}</imgcaption>
-Specific settings pertaining to the the way the loop filters are engaged to obtain the optical lock are available in the Loop Filters bar at the bottom of the Optical lock tab. It is not advised that the settings for this section be changed from their default values. Doing so could affect your ability to obtain a stable lock.
-====Dither====
-The Dither tab allows the user to add a modulation to the DAC current. Each DAC can individually be configured to be modulated at a specific frequency, integration time, and amplitude. A checkbox below these fields allows the user to select whether the modulation is always on (Manual On), always off (Manual Off), or to allow the computer to determine when the modulation is applied (Automatic).
-====Slow Loop====
+=====Slow Loop=====
 ===Firmware Version FL-V1.2===
-The Slow Loop tab allows the user to enable a slow servo temperature control of the intracavity PZT to prevent offset drift over long periods of time. It is recommended to always enable this feature after setting up a lock, as without it the PZT's offset voltage can drift to its rails over the course of several hours or even less. To enable the Slow Loop feature, simply fill in the "FFC COM Port:" field with the number corresponding to your FFC-100's COM port, choose the desired setpoint of the PZT, and press the "Activate Temperature Slow Loop" button at the top of the tab. For example, if your FPGA is on COM4, and your FFC-100 is on COM8, type "8" into the "FFC Com Port:" field and then press the button. This will bring up a command prompt window which will display information about the Slow Loop, such as the cavity temperature, and the current PZT setpoint. In general, it is best to select a setpoint near the center of the PZT's available range.
+The Slow Loop tab of either the the SLICE-FPGA allows the user to enable a slow servo temperature control of the intracavity PZT to prevent offset drift over long periods of time. It is recommended to always enable this feature after setting up a lock, as without it the PZT's offset voltage can drift to its rails over the course of several hours or even less. To enable the Slow Loop feature, simply fill in the "FFC COM Port:" field with the number corresponding to your FFC-100's COM port, choose the desired setpoint of the PZT, and press the "Activate Temperature Slow Loop" button at the top of the tab. For example, if your FPGA is on COM4, and your FFC-100 is on COM8, type "8" into the "FFC Com Port:" field and then press the button. This will bring up a command prompt window which will display information about the Slow Loop, such as the cavity temperature, and the current PZT setpoint. In general, it is best to select a setpoint near the center of the PZT's available range.
-<WRAP center round important 100%>To determine the COM port of your FFC, open the Windows Device Manager on your PC, expand the "Ports (COM & LPT)" drop down, take note of which COM ports are listed, then unplug the FFC-100's USB connection. After the list updates, the COM port of the FFC-100 will no longer be listed.
+<WRAP center round important 100%>To determine the COM port of your FFC-100, open the Windows Device Manager on your PC, expand the "Ports (COM & LPT)" drop down, take note of which COM ports are listed, then unplug the FFC-100's USB connection. After the list updates, the COM port of the FFC-100 will no longer be listed.
 </WRAP>
 ===Firmware Version G2-V1.2===