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d2:offset_phase_lock_servo

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d2:offset_phase_lock_servo [2019/11/20 02:01] – [Options] Michael Radunskyd2:offset_phase_lock_servo [2019/11/20 02:07] – [Monitor Section] Michael Radunsky
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 =====Modes===== =====Modes=====
  
-The OPLS operates in 12 different modes, controlled by the front-panel knob or with external inputs to the back-panel. These 12 modes select the value of the divide-by-N (N=8,16,32, or 64) and select between three states for the reference frequency (external input, internal VCO High, internal VCO Low).  The table below shows the offset frequency ranges for these 12 different modes.+The OPLS operates in 12 different modes, controlled by the front-panel knob or with external inputs to the back-panel. These 12 modes select the value of the divide-by-N (N=8, 16, 32, or 64) and select between three states for the reference frequency (external input, internal VCO High, internal VCO Low).  The table below shows the offset frequency ranges for these 12 different modes.
  
 <WRAP center round box 70%> <WRAP center round box 70%>
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 ^ ^^  N=8  ^  N=16  ^  N=32  ^  N=64  ^ ^ ^^  N=8  ^  N=16  ^  N=32  ^  N=64  ^
 ^  Reference \\ Frequency \\ Setting  ^External |250 - 1,920|480 - 3,840|960 - 7,680|1,920 - 10,000| ^  Reference \\ Frequency \\ Setting  ^External |250 - 1,920|480 - 3,840|960 - 7,680|1,920 - 10,000|
-^:::^External Reference Input Frequency |30 - 240||||+^:::^External Reference Input Frequency |30 - 240 MHz||||
 ^:::^Internal VCO Low |385 - 850|770 - 1,700|1,540 - 3,400|3,080 - 6,800| ^:::^Internal VCO Low |385 - 850|770 - 1,700|1,540 - 3,400|3,080 - 6,800|
 ^:::^Internal VCO High |770 - 1,700|1,540 - 3,400|3,080 - 6,800|6,160 - 10,000| ^:::^Internal VCO High |770 - 1,700|1,540 - 3,400|3,080 - 6,800|6,160 - 10,000|
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 ===Error Signal (AC)=== ===Error Signal (AC)===
  
-This is an unfiltered version of  Error Signal (DC) that is four times smaller, and has a DC offset.  When phase locked, the output is 1.6V+2.8<sup>mv</sup>/<sub>deg</sub>*θ, where θ is the phase-error in degrees. When in frequency mode, the output is 1.6V±1V*(1-f<sub>small</sub>/(2 f<sub>big</sub>)).+This is an unfiltered version of  Error Signal (DC) that is four times smaller, and has a DC offset.  When phase locked, the output is 1.6V+2.8<sup>mV</sup>/<sub>deg</sub>*θ, where θ is the phase-error in degrees. When in frequency mode, the output is 1.6V±1V*(1-f<sub>small</sub>/(2 f<sub>big</sub>)).
  
 ===Ref Freq=== ===Ref Freq===
d2/offset_phase_lock_servo.txt · Last modified: 2023/11/16 00:02 by 127.0.0.1