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| ffc:locking_electronics:slice-fpga-ii [2023/06/09 21:26] – external edit 127.0.0.1 | ffc:locking_electronics:slice-fpga-ii [2023/07/05 17:44] – external edit 127.0.0.1 |
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| Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\ | Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\ |
| Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\ | Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\ |
| Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\ | /*Click here for the [[ffc:100m|FFC-100 Fiber Frequency Comb Manual]]\\ */ |
| Click here for the [[ffc:100:API|FFC-100 API]].\\ | Click here for the [[ffc:100:API|FFC-100 API]].\\ |
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| - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:updated_locking_fopt.png?800 |}}</imgcaption>\\ | - Press the “Lock” button (<imgref fopt_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. A warning may occur if the selected VCO sign is incorrect. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom center).<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:updated_locking_fopt.png?800 |}}</imgcaption>\\ |
| - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC. | - If the Beatnote is properly locked, the integrated phase noise value listed in the center of the window should be close to the value listed in your devices CoC. |
| - Adjust PID settings (bottom of <imgref fceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment. | - Adjust PID settings (bottom of <imgref ceo_lock> and <imgref fopt_lock>) as needed to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are tuned for your specific device but tweaking the values can often improve performance based on the noise characteristics of your environment. |
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| =====Troubleshooting===== | =====Troubleshooting===== |
| ====Overview==== | ====Overview==== |
| In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython Spyder environment. | In many cases, all that is necessary to get up-and-running with the SLICE-FPGA-II is to install the correct WinPython distribution, and run the provided GUI software using the WinPython terminal. |
| If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure. | If you are unable to connect the GUI to the SLICE-FPGA-II, follow the below instructions to eliminate possible causes of failure. |
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