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--- ffc:locking_electronics:rpm-100 [2022/09/26 23:59] – external edit 127.0.0.1
+++ ffc:locking_electronics:rpm-100 [2022/09/27 20:27] – external edit 127.0.0.1
@@ Line 9: / Line 9: @@
 Please read [[:limited_warranty|Limited Warranty]] and [[:warnings_cautions|General Warnings and Cautions]] prior to operating the RPM-100.
-====Links====
+=====Links=====
 Click here for the [[http://www.vescent.com/manuals/doku.php?id=manuals|Main Manuals Page]].\\
 Click here for the [[ffc:100|FFC-100 Quick Start Guide]].\\
@@ Line 67: / Line 67: @@
 <imgcaption front_panel|Front Panel of the RPM-100>{{ :ffc:locking_electronics:front_panel_markup.png?600 |}}</imgcaption>
-  -Placeholder
+  -f<sub>CEO</sub> input signal SMA
-  -Placeholder
+  -f<sub>OPT</sub> input signal SMA
-  -Placeholder
+  -Current output for modulating pump diode on the FFC-100
-  -Placeholder
+  -PZT modulation output
-  -Placeholder
+  -Output for feeding an external reference clock, which can improve 10MHz timing on onboard oscillator. Use requires specifying input frequency in the settings menu.
 =====Back Panel=====
-{{ :ffc:locking_electronics:back_panel_markup.png?600 |}}
+<imgcaption back_panel|Back Panel of the RPM-100>{{ :ffc:locking_electronics:back_panel_markup.png?600 |}}</imgcaption>
-  -Placeholder
+  -AC power entry module and fuse
-  -Placeholder
+  -Currently Unused Extension port
-  -Placeholder
+  -Reference Clock signal (+3V 10MHz) for clocking external equipment
-  -Placeholder
+  -Analog Slow Servo control voltage (±10V)
-  -Placeholder
+  -Ethernet port for communication with a computer
+=====Software Setup=====
+  * Open the “WinPython-64bit-3.6.1.0Qt5” folder after installing WinPython, and launch the Spyder application within this folder.
+  * Open the “digital_servo_python_gui_RPM100” folder and locate the GUI control file named “XEM_GUI3.py”.
+  * Drag and drop the file into Spyder, and run the script to launch the GUI.
+  * A start-up menu should appear (figure ??). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK.
+{{ :ffc:locking_electronics:start_window_marked.png?600 |}}
+  * Navigate to the “Settings” tab and select the appropriate clock signal to be used. If using an external clock, type the frequency (in Hz) of your reference signal.
+{{ :ffc:locking_electronics:settings_marked.png?600 |}}
-====FPGA Control====
+=====FPGA Control=====
 The RPM-100 FPGA Controller can be used to phase lock ƒ<sub>CEO</sub> to a reference and ƒ<sub>OPT</sub> to a reference laser such as the Rio Planex.
@@ Line 95: / Line 106: @@
-====Software Setup====
-  * Open the “WinPython-64bit-3.6.1.0Qt5” folder after installing WinPython, and launch the Spyder application within this folder.
-  * Open the “digital_servo_python_gui_RPM100” folder and locate the GUI control file named “XEM_GUI3.py”.
-  * Drag and drop the file into Spyder, and run the script to launch the GUI.
-  * A start-up menu should appear (figure ??). Check that the software can recognize the ethernet connection to the module. If the module is recognized, the device name and IP address will appear next to “Connected FPGAs”. If the device is not initially found, click “Broadcast discovery packet” to search for the device. Ensure “Push default values to Red Pitaya” is selected and press OK.
-{{ :ffc:locking_electronics:start_window_marked.png?600 |}}
-  * Navigate to the “Settings” tab and select the appropriate clock signal to be used. If using an external clock, type the frequency (in Hz) of your reference signal.
-{{ :ffc:locking_electronics:settings_marked.png?600 |}}
 ==== Locking ƒ(CEO) ====
-  - Navigate to the “CEO Lock” tab and adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the the data in the Baseband IQ plot is circular (<imgref ceo_bbiq>).  This centers the beat note near the reference frequency.  It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment.\\ <imgcaption ceo_bbiq|Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)>{{ ffc:fpga_ceo_lock.png?800  |ffc:fpga_ceo_lock.png}}</imgcaption>\\
+  - Navigate to the “CEO Lock” tab and adjust the “Offset DAC 0” slider near the top left by clicking and dragging the slider until the the data in the Baseband IQ plot is circular and the beat note is visibly centered under the middle red filter arch (<imgref ceo_bbiq>). It is also possible to adjust the FFC-100 oscillator current on its front panel to make this adjustment.\\ <imgcaption ceo_bbiq|Centering ƒ(CEO) on reference frequency (Baseband IQ optimization)>{{ :ffc:locking_electronics:fceo_2_centered.png?800 |}}</imgcaption>\\
-  - Press the “Lock” button (<imgref ceo_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom left).\\ <imgcaption ceo_lock|Locking ƒ(CEO)>{{ ffc:fpga_ceo_lock_2.png?800  |ffc:fpga_ceo_lock_2.png}}</imgcaption>\\
+  - Press the “Lock” button (<imgref ceo_lock>, top middle). If the system doesn’t lock, change the VCO sign to the opposite polarity (top right) and try again. If the system still won't lock, try lowering the K<sub>p</sub> value (bottom left).\\ <imgcaption ceo_lock|Locking ƒ(CEO)>{{ :ffc:locking_electronics:fceo_3_locked.png?800 |}}</imgcaption>\\
 ====Locking ƒ(opt)====
-  - Navigate to the “Optical Lock” window.  Center the beat note near the reference frequency: adjust the “Offset DAC 1” slider (or your reference laser frequency) until you see a circular Baseband IQ diagram (<imgref opt_bbiq>).\\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>{{ ffc:fpga_optical_bbiq.png?800  |ffc:fpga_optical_bbiq.png}}</imgcaption>\\
+  - Navigate to the “Optical Lock” window.  Center the beat note near the reference frequency: adjust the “Offset DAC 1” slider (or your reference laser frequency) until you see a circular Baseband IQ diagram (<imgref opt_bbiq>).\\ <imgcaption opt_bbiq|Centerig ƒ(opt) on reference frequency (Baseband IQ optimization)>
-  - Press the “Lock” button (<imgref fopt_lock>). If ƒ<sub>opt</sub> doesn’t lock, change the VCO sign to the opposite polarity and try again. If the system continues to not lock, lower the K<sub>p</sub> value.\\<imgcaption fopt_lock|Locking ƒ(opt)>{{ ffc:fpga_optical_lock.png?800  |ffc:fpga_optical_lock.png}}</imgcaption>\\
+{{ :ffc:locking_electronics:fopt_1_no-lock.png?800 |}}</imgcaption>\\
+  - Press the “Lock” button (<imgref fopt_lock>). If ƒ<sub>opt</sub> doesn’t lock, change the VCO sign to the opposite polarity and try again. If the system continues to not lock, lower the K<sub>p</sub> value.<imgcaption fopt_lock|Locking ƒ(opt)>{{ :ffc:locking_electronics:fopt_2_locked.png?800 |}}</imgcaption>\\
   - Adjust PID settings (bottom middle of <imgref fopt_lock>) accordingly to lower the integrated phase noise of each parameter (f<sub>CEO</sub> and f<sub>opt</sub>). The default settings provided in the software are a good place to start but tweaking the values can often improve performance.
+====External Clock====
+The external clock input (#5 on the [[ffc:locking_electronics:rpm-100#Front Panel|Front Panel Diagram]]) is used to feed an external reference clock, which can be used to clock the RPM-100s ADCs and generate the 10MHz reference signal which is normally generated with the internal oscillator. For example, the RPM-100 can be clocked with an external reference, or the f<sub>REP</sub> signal from the FFC-100. To use this feature, it is necessary to first specify the input frequency in the settings menu of the software provided with the RPM-100, under the "Target ExtClk Freq" box. Pressing ENTER after giving a value will apply the new clock settings.
+<imgcaption settings|The settings screen of the RPM-100>{{ :ffc:locking_electronics:settings.png?800 |}}</imgcaption>
+The RPM-100 will attempt to use the specified frequency, however, due to the limitations of the FPGA's Peak Locked Loop hardware, certain frequencies work better than others. For example, frequencies such as 25MHz, 50MHz, 75MHz, 100MHz, 125MHz, or 200MHz will result in exact clocking and a clean 10MHz output signal. Unusual frequencies such as 42.3MHz cannot be used to produce a precise ADC clock or 10MHz reference.
 =====Troubleshooting=====
 ====Overview====