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--- ffc:comb_module_quickstart [2021/12/07 18:42] – external edit 127.0.0.1
+++ ffc:comb_module_quickstart [2022/04/01 15:58] – external edit 127.0.0.1
@@ Line 6: / Line 6: @@
 {{d2:d2-100:class_iiib.png?nolink&200}}
-<imgcaption ffc|The SVS FFC Module with a coffee mug for scale>{{ :ffc:microsoftteams-image.png?350|}}</imgcaption>
+<imgcaption ffc|The FFC-CM with a coffee mug for scale>{{ :ffc:microsoftteams-image.png?350|}}</imgcaption>
 ====Useful Links====
 [[http://www.vescent.com/manuals/doku.php?id=manuals|Vescent manuals page]].\\
-[[ffc:100:api|FFC-100 API]].\\
+[[ffc:cm:api-ld|FFC-CM Laser Driver API]].\\
-[[https://www.vescent.com/products/lasers/ffc-100-frequency-comb/|FFC-100 web page]].\\
+[[ffc:cm:api-osc|FFC-CM Fiber Laser/Oscillator API]].\\
+[[https://www.vescent.com/products/lasers/ffc-100-frequency-comb/|FFC-CM web page]].\\
 [[https://github.com/Vescent/FFC_Firmware_Upgrade-and-FPGA-Software-Firmware|Github page for FFC-100 firmware revisions]]
 [[https://www.vescent.com/manuals/doku.php?id=ffc:100m|FFC-100 Manual]]\\
@@ Line 22: / Line 23: @@
 ===== Proper Usage =====
 | {{ :warning-sign.png?100&nolink }}  | If this instrument is used in a manner not specified by the manufacturer in this manual or other relevant literature, protection provided by the instrument may be impaired. |
-|:::| Successful implementation of the SVS FFC Module depends critically on the design of the whole system: SVS FFC Module, phase locking electronics, and any references to which the SVS FFC Module is locked or //vice versa//. |
+|:::| Successful implementation of the FFC-CM depends critically on the design of the whole system: FFC-CM, phase locking electronics, and any references to which the FFC-CM is locked or //vice versa//. |
 =====Purchase Includes=====
@@ Line 44: / Line 45: @@
-=====Operating the SVS FFC Module=====
+=====Operating the FFC-CM=====
-This document provides basic instructions on how to operate the Vescent Photonics SVS Fiber Frequency Comb Module in conjunction with the Vescent SLICE-FPGA. It is important to note that the SVS FFC Module itself does not come with a built in GUI, and as such communication must be done through the [[link|Serial Command API]] or the [[link|FPGA Software]]. This document will walk through usage of the Serial Command interface including  several basic commands, as well as using the FPGA Software to obtain and optimize your lock.
+This document provides basic instructions on how to operate the Vescent Photonics SVS Fiber Frequency Comb Module in conjunction with the Vescent SLICE-FPGA. It is important to note that the FFC-CM itself does not come with a built in GUI, and as such communication must be done through the [[ffc:cm:api-osc|Serial Command API]] or the [[ffc:comb_module_quickstart #FPGA Control|FPGA Software]]. This document will walk through usage of the Serial Command interface including  several basic commands, as well as using the FPGA Software to obtain and optimize your lock.
 =====System Set-up=====
 ====Initial Connections====
-To begin, connect the SVS FFC Module to power, turn it on, then connect it to a Windows 10 computer using the included USB Type-B to USB Type-A connector. The next few steps will walk through installing and verifying the SSH software required to communicate with the SVS FFC Module.
+To begin, connect the FFC-CM to power, turn it on, then connect it to a Windows 10 computer using the included USB Type-B to USB Type-A connector. The next few steps will walk through installing and verifying the SSH software required to communicate with the FFC-CM.
 ====Serial Command Interface====
-To use the SVS FFC Module, you will first need to install SSH software for communicating via serial commands. Vescent recommends using either [[https://ttssh2.osdn.jp/index.html.en|Tera Term]] or [[https://www.putty.org/|PuTTy]], but there are a variety of other options. This guide will focus on connecting to the SVS FFC Module using Tera Term.
+To use the FFC-CM, you will first need to install SSH software for communicating via serial commands. Vescent recommends using either [[https://ttssh2.osdn.jp/index.html.en|Tera Term]] or [[https://www.putty.org/|PuTTy]], but there are a variety of other options. This guide will focus on connecting to the FFC-CM using Tera Term.
 ===Installing SSH Software===
@@ Line 74: / Line 75: @@
 ===Sending Commands===
 With the Serial Command interface set up now, you will be able to send individual commands to the SVS FFC Module by typing them directly into the terminal. During the initial verification and test setup of the SVS FFC Module, it is recommended to use the terminal interface as shown in this guide, though later it may be beneficial to write your own serial command scripts.
+====FPGA Control====
+The SLICE-FPGA dual-channel Offset Phase Lock Servo can be used to phase lock ƒ<sub>CEO</sub> and ƒ<sub>opt</sub>. Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All performance data is collected with a Rio Planex laser.
 ===Installing FPGA Software===
@@ Line 86: / Line 90: @@
 <imgcaption about|Check whether your operating system is 32-bit or 64-bit>{{ :ffc:about.png?500 |}}</imgcaption>
+Open the WinPython folder and navigate to the site-packages directory: ''...\WPy64-3950\python-3.9.5.amd64\Lib\site-packages''. In a new window, open the FPGA Software folder and locate the file "ok". Copy this file from FPGA Software into the site-packages directory of WinPython. Close the WinPython folder, and open a command line or terminal. Navigate to the ''...\FPGA Software\FPGA Software'' directory in the terminal and run the command ''pip install PyVISA-1.8-py2.py3-none-any.whl''.
+<imgcaption pyvisa|A successful installation will look like this. >{{ :ffc:pyvisa_install.png?500 |}}</imgcaption>
+Finally, go back to the FPGA Software folder in your file explorer and run both "FrontPanelUSB-Win-x64-4.5.6", and "vcredist_x64". Each will open their own installer. Follow the instructions on both and click finish. When both are done installing, your computer should be configured to run the FPGA software.
 =====Locking the SVS FFC Module=====
-Before locking, it may be beneficial to familiarize yourself with the full list of API commands for the SVS FFC Module, which can be found [[link|here]], as well as the front and rear panel connections, which can be found [[link|here]]. It is also important to note that, aside from those set in the FPGA software, all PID parameters come preset and should not need to be adjusted.
+Before locking, it may be beneficial to familiarize yourself with the full list of API commands for the SVS FFC Module, which can be found [[ffc:cm:api-osc|here]], as well as the front and rear panel connections, which can be found in Figure 8. It is also important to note that, aside from those set in the FPGA software, all PID parameters come preset and should not need to be adjusted.
 ===Connections===
@@ Line 118: / Line 126: @@
 ===Step 5: Verify Supercontinuum===
-Now that the system is mode locked, switch the monitored output to SC Out and change your Spectrum Analyzer or OSA's window to span the 1-2 micron wavelength region. Verify that the supercontinuum of your system matches that shown in your CoC. An example supercontinuum can be seen in <imgref SC>
+Now that the system is mode locked, turn on the EDFA/AMP pump diode and switch the monitored output to SC Out. Change your Spectrum Analyzer or OSA's window to span the 1-2 micron wavelength region and verify that the supercontinuum of your system matches that shown in your CoC. An example supercontinuum can be seen in <imgref SC>
 <imgcaption SC|Example supercontinuum of the SVS FCC Module system>{{ :ffc:boeingffc_system1_scout.png?400 |}}</imgcaption>
@@ Line 136: / Line 144: @@
 <imgcaption PID|Location of CEO Lock PID parameter input fields>{{ :ffc:ceo_lock_pid_parameters.png?600 |}}</imgcaption>
+===Step 8: CEO Lock===
+Begin by navigating to the CEO Lock tab, then ensure that there is a visible beatnote displayed on the “Spectrum” plot. This will be an obvious peak above the noise floor which responds to adjustments of the “Offset DAC 0 [V]” slider as shown in <imgref CEO_1>. If a beatnote cannot be identified, check that the SVS FFC Module is still mode locked. Once a beatnote has been identified, adjust the “Offset DAC 0 [V]” slider such that the Baseband IQ plot is roughly circular, or the identified beatnote is between two of the dips on the spectrum plot corresponding to a bandpass filter.
+<imgcaption CEO_1|Offset DAC location and Beatnote Example>{{ :ffc:ceo_lock_pt_1.png?600 |}}</imgcaption>
+Determine the VCO sign of the system by very slightly increasing the "Offset DAC 0 [V]" slider. If the beatnote moves to the right the sign is positive. If it moves to the left the sign is negative. Check the appropriate VCO Sign checkbox shown in <imgref checkbox>, then press the "Lock" button. The system should quickly lock up, but if it does not check the opposite VCO sign check box and try again. If the system still does not lock, double check that the PID parameters were set to the values shown in your CoC.
-=====FPGA Control=====
+<imgcaption checkbox|Location of the VCO Sign Checkboxes, and the "Lock" button.>{{ :ffc:ceo_lock_pt_2.png?600 |}}</imgcaption>
-The SLICE-FPGA dual-channel Offset Phase Lock Servo can be used to phase lock ƒ<sub>CEO</sub> and ƒ<sub>opt</sub>. Locking f<sub>opt</sub> requires a reference CW laser and heterodyne setup (such as a 50:50 beam splitter and DWDM filter). The stability of the lock will depend on the reference laser used. All performance data is collected with a Rio Planex laser.
-If you have not already done so, [[ffc:fpga|install Python and the FPGA software]] for controlling the SLICE-FPGA dual Offset Phase Lock Servo.
+Once a lock has been obtained, the green plot of phase noise on the “Phase Noise PSD, std dev =” plot will show a dramatic reduction in noise from ƒCEO's unlocked state. This number is a good characterization of the stability of your lock. A good lock of ƒCEO is indicated by an integrated phase noise PSD less than 2 rad, but this value can be pushed down even further by adjusting the PID settings of your FFC-100.
+Before adjusting the PID parameters, uncheck “Auto-refresh” at the top of the screen. Change the value of “RBW: 576 Hz; Points:” to “3e6”, then recheck “Auto-refresh” (figure 34). This will update the graph to plot more points and give a more accurate representation of the phase noise. It is important that Auto-Refresh be unchecked before making this adjustment, however, as doing so while the plot is refreshing may cause the FPGA software to crash. If this happens, simply relaunch the software and start again.